Contact area design for solder bonding

Patent metadata

Field	Value
Publication number	US-2016190082-A1
Application number	US-201414584748-A
Country	US
Kind code	A1
Filing date	Dec 29, 2014
Priority date	Dec 29, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.

First claim

What is claimed is:

1 . A package comprising:
a first package component comprising:
a first dielectric layer;
a metal pad over the first dielectric layer; and
a first plurality of openings in the metal pad, wherein the first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.

2 . The package of claim 1 further comprising:
a second package component comprising a metal pillar; and
a solder region bonding the metal pillar to the metal pad, wherein the solder region extends into the first plurality of openings to contact sidewalls of the metal pad, with the sidewalls of the metal pad in the first plurality of openings.

3 . The package of claim 1 further comprising:
a metal trace coplanar with, and connected to, the metal pad, wherein a bottom surface of the metal pad is in contact with a top surface of a dielectric material.

4 . The package of claim 1 further comprising a metal trace in the first dielectric layer, wherein the metal trace comprises:
a trace portion having a first width; and
a pad portion having a second width greater than the first width, wherein the metal pad overlies and contacts the pad portion of the metal trace.

5 . The package of claim 4 , wherein the pad portion of the metal trace is a solid pad with no opening therein.

6 . The package of claim 4 , wherein the pad portion of the metal trace comprises a second plurality of openings, with the second plurality of openings filled with a dielectric material.

7 . The package of claim 6 , wherein each of the second plurality of openings is overlapped by one of the first plurality of openings.

8 . The package of claim 1 further comprising a second dielectric layer comprising a portion coplanar with the metal pad, wherein the second dielectric layer comprises a top surface higher than a top surface of the metal pad.

9 . The package of claim 1 , wherein a top surface of the first dielectric layer is exposed.

10 . A package comprising:
a first package component comprising:
a metal pad, wherein the metal pad comprises a plurality of discrete portions physically separated from each other, wherein the plurality of discrete portions is electrically coupled to each other.

11 . The package of claim 10 wherein bottoms of the plurality of discrete portions of the metal pad are in contact with a dielectric material.

12 . The package of claim 10 further comprising:
a solder region physically contacting one of the plurality of discrete portions of the metal pad, and physically disconnected from remaining ones of the plurality of discrete portions of the metal pad; and
a via interconnecting the plurality of discrete portions of the metal pad.

13 . The package of claim 10 further comprising a continuous solder region joining the plurality of discrete portions of the metal pad.

14 . The package of claim 10 further comprising a metal trace under the metal pad, wherein the metal trace comprises:
a trace portion having a first width; and
a pad portion having a second width greater than the first width, wherein the metal pad overlies and contacts the pad portion of the metal trace.

15 . The package of claim 14 , wherein the pad portion of the metal trace is a solid pad with no opening therein.

16 . The package of claim 14 , wherein the pad portion of the metal trace comprises an additional plurality of discrete portions, with each of the plurality of discrete portions of the metal pad overlapping and contacting a corresponding one of the additional plurality of discrete portions of the pad portion of the metal trace.

17 . The package of claim 10 , wherein an entirety of a bottom surface of the metal pad is in contact with a top surface of a dielectric layer.

18 . A package comprising:
a first package component comprising:
a metal trace comprising a trace portion and a pad portion connected to the trace portion, wherein the pad portion is wider than the trace portion;
a metal pad overlapping and in contact with the pad portion; and
a first plurality of openings in the metal pad, wherein the first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region;
a second package component; and a solder region bonding the second package component to the metal pad.

19 . The package of claim 18 , wherein the first plurality of openings comprises through-openings penetrating through the metal pad.

20 . The package of claim 18 , wherein the pad portion of the metal trace comprises a second plurality of openings, with the second plurality of openings filled with a dielectric material.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Tsai Pei-Chun
• Chen Yu-Feng
• Kuo Tin-Hao
• Chen Chen-Shien

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/07253

  changes in shapes · CPC title

• H10W72/07236

  Soldering or alloying · CPC title