MOSFET with ultra low drain leakage

Patent metadata

Field	Value
Publication number	US-10164014-B2
Application number	US-201615287854-A
Country	US
Kind code	B2
Filing date	Oct 7, 2016
Priority date	Jul 30, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

First claim

The invention claimed is:

1. A method for forming a transistor, comprising:
forming a passivation layer on a monocrystalline substrate;
forming a gate conductor on the passivation layer over a portion of the substrate to define a channel region;
etching recesses in the substrate through the passivation layer on opposite sides of the channel region, each of the recesses extending below a portion of the passivation layer to form undercut regions below the gate conductor and below the passivation layer on a side opposite the undercut region below the gate conductor;
depositing a dielectric material to form a dielectric pad on a bottom of each of the recesses, wherein each of the dielectric pads does not contact the sidewalls in the undercut regions; and
forming an n-type source/drain material in each of the recesses, wherein the source/drain material is formed on one of the dielectric pads, and the source/drain material makes contact with the recess sidewalls in the undercut regions.

2. The method as recited in claim 1 , wherein the n-type source/drain material includes Al-doped ZnO.

3. The method as recited in claim 1 , wherein the dielectric material is evaporated at a 90 degree incidence to prevent the dielectric material from forming on the sidewalls of the recesses.

4. The method as recited in claim 1 , wherein the n-type material is deposited directly on the dielectric pads.

5. The method as recited in claim 1 , wherein forming the source/drain material utilizes atomic layer deposition.

6. The method as recited in claim 1 , wherein the n-type material includes an amorphous phase.

7. The method as recited in claim 1 , wherein the dielectric pads cover only a portion of the bottom of each of the recesses, and the n-type source/drain material covers a portion of the bottom of each of the recesses.

8. The method as recited in claim 7 , wherein the passivation layer masks a portion of the bottom of each of the recesses.

9. The method as recited in claim 1 , wherein depositing the dielectric material further forms a gate cap dielectric on a portion of the gate conductor.

10. The method as recited in claim 9 , wherein the gate cap dielectric is also on a portion of the passivation layer.

11. A method for forming a transistor, comprising:
forming a passivation layer on a substrate;
patterning the passivation layer to expose portions of the substrate on opposite sides of a channel region;
forming a gate conductor on the passivation layer over the channel region;
etching recesses in the substrate, wherein a portion of each of the recesses extends below a portion of the passivation layer to form undercut regions below the passivation layer;
depositing a dielectric material on a portion of the bottom of each of the recesses to form a dielectric pad, wherein the passivation layer masks a portion of each of the recesses, and the dielectric material is evaporated at a 90 degree incidence, so the dielectric material does not contact the sidewalls in the undercut regions; and
forming a source/drain material in each of the recesses.

12. The method as recited in claim 11 , wherein the source/drain material is an amorphous n-type material.

13. The method as recited in claim 12 , wherein the substrate is a III-V material.

14. The method as recited in claim 11 , further comprising patterning the gate conductor, wherein the gate conductor is patterned using a lift-off layer (LOL) gate lithography process.

15. The method as recited in claim 11 , wherein the source/drain material contacts a bottom surface of the recesses and a sidewall adjacent to the channel region.

16. A method for forming a transistor, comprising:
forming a passivation layer on a monocrystalline substrate;
forming a gate conductor on the passivation layer;
removing portions of the passivation layer on opposite sides of the gate conductor to expose portions of the monocrystalline substrate;
etching recesses in the substrate on opposite sides of the gate conductor, wherein a portion of each of the recesses extends below a portion of the gate conductor, and defines a channel region between the recesses and below the gate conductor;
depositing a dielectric material on a portion of the bottom surface of each of the recesses to form a dielectric pad in each of the recesses, wherein each of the dielectric pads are not in contact with the sidewall surface of the recess; and
depositing source/drain material in each of the recesses in contact with the bottom surface and the sidewall surface of the recess.

17. The method as recited in claim 16 , wherein the channel region is a III-V material, and the source/drain material in each of the recesses is a II-VI material.

18. The method as recited in claim 16 , wherein the source/drain material is deposited by atomic layer deposition (ALD).

19. The method as recited in claim 16 , wherein the source/drain material is crystalline.

20. The method as recited in claim 16 , further comprising forming an electrical contact on each of the source/drain material in each of the recesses.

Assignees

• IBM

Inventors

• De Souza Joel P
• Fogel Keith E
• Kim Jeehwan
• Sadana Devendra K

Classifications

• H10P14/3442

  N-type · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10D64/01358

  the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material · CPC title