Transistor(s) with different source/drain channel junction characteristics, and methods of fabrication

Patent metadata

Field	Value
Publication number	US-9230802-B2
Application number	US-201414282094-A
Country	US
Kind code	B2
Filing date	May 20, 2014
Priority date	May 20, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Field-effect transistors (FETs) and methods of fabricating field-effect transistors are provided, with one or both of a source cavity or a drain cavity having different channel junction characteristics. The methods include, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of the transistor, the recessing defining a bottom channel interface surface and a sidewall channel interface surface within the cavity; providing a protective liner over the sidewall channel interface surface, with the bottom channel interface surface being exposed within the cavity; processing the bottom channel interface surface to facilitate forming a first channel junction of the transistor; and removing the protective liner from over the sidewall channel interface surface, and subsequently processing the sidewall channel interface surface to form a second channel junction of the transistor, where the first and second channel junctions have different channel junction characteristics.

First claim

What is claimed is:

1. A method of fabricating field effect transistors (FETs), the method comprising:
recessing a semiconductor material to form a cavity therein adjacent to a channel region of a transistor, the recessing defining a first channel interface surface and a second channel interface surface within the cavity;
providing a protective liner over the second channel interface surface within the cavity, with the first channel interface surface being exposed within the cavity;
processing the first channel interface surface to facilitate forming a first channel junction of the transistor at the first channel interface surface within the cavity; and
removing the protective liner from over the second channel interface surface, and processing the second channel interface surface to form a second channel junction of the transistor at the second channel interface surface within the cavity, wherein the first channel junction of the transistor and the second channel junction of the transistor comprise one or more different channel junction characteristics.

2. The method of claim 1 , wherein processing the first channel interface surface within the cavity facilitates forming a first channel buffer region, and processing the second channel interface surface within the cavity comprises forming a second channel buffer region within the cavity.

3. The method of claim 2 , wherein processing the first channel interface surface within the cavity comprises epitaxially growing at least a first portion of the first buffer channel region within the cavity, and wherein processing the second channel interface surface within the cavity comprises epitaxially growing the second channel buffer region within the cavity.

4. The method of claim 3 , wherein processing the second channel interface surface within the cavity further comprises epitaxially growing a second portion of the first channel buffer region over the first portion thereof at the first channel interface surface commensurate with epitaxially growing the second channel buffer region.

5. The method of claim 4 , wherein the first channel buffer region and the second channel buffer region have different thicknesses.

6. The method claim 4 , wherein the first channel buffer region and the second channel buffer region comprise one or more different epitaxial material characteristics.

7. The method of claim 3 , further comprising, after the providing the protective liner over the second channel interface surface, further recessing the first channel interface surface within the cavity to accommodate the epitaxial growing of the first portion of the first buffer channel region within the cavity without overlying the protective liner.

8. The method of claim 1 , wherein processing the first channel interface surface within the cavity comprises performing a first implant of the first channel interface surface within the cavity to facilitate forming the first channel junction of the transistor, and processing the second channel interface surface within the cavity comprises performing a second implant of the second channel interface surface to form the second channel junction of the transistor.

9. The method of claim 8 , wherein performing the second implant also comprises further implanting the first channel interface surface to form the first channel junction of the transistor from the first implant and the second implant.

10. The method of claim 1 , wherein the first channel interface surface comprises a bottom channel interface surface within the cavity, and the second channel interface surface comprises a sidewall channel interface surface within the cavity.

11. The method of claim 1 , further comprising forming one of a source region or a drain region within, at least partially, the cavity subsequent to forming of the first and second channel junctions therein.

12. The method of claim 1 , wherein the protective liner over the second channel interface surface comprises at least one of a nitride or an oxide liner.

13. The method of claim 1 , wherein the cavity comprises a first cavity, and the recessing of the semiconductor material further comprises forming a second cavity therein adjacent to the channel region of the transistor, and wherein the first channel interface surface comprises a bottom channel interface surface within the first cavity, and the second channel interface surface comprises a sidewall channel interface surface within the first cavity, and wherein the method further comprises:
providing the protective liner over a sidewall channel interface surface within the second cavity, with a bottom channel interface surface within the second cavity being exposed;
simultaneously processing the bottom channel interface surfaces within the first and second cavities to facilitate forming first channel junctions of the transistor within the first and second cavities at the bottom channel interface surfaces thereof;
removing the protective liner from over the sidewall channel interface surfaces within the first and second cavities, and subsequently, simultaneously processing the sidewall channel interface surfaces within the first and second cavities to facilitate forming the second channel junctions of the transistor at the sidewall channel interface surfaces of the first and second cavities, wherein the first channel junction and the second channel junction within each cavity of the first and second cavities comprise different channel junction characteristics; and
forming a source region of the transistor at least partially within the first cavity, and a drain region of the transistor at least partially within the second cavity.

14. A device comprising:
a transistor, the transistor comprising:
a source region and a drain region separated by a channel region, the channel region residing within a semiconductor material; and
wherein at least one of the source region or the drain region resides, at least partially, within a cavity in the semiconductor material, with the cavity comprising a first channel junction of the transistor at a bottom channel interface surface of the cavity, and a second channel junction of the transistor at a sidewall channel interface surface of the cavity, wherein the first channel junction of the transistor and the second channel junction of the transistor comprise one or more different channel junction characteristics.

15. The device of claim 14 , wherein the source region and the drain region each reside, at least partially, within a respective cavity in the semiconductor material, and wherein the respective cavity comprises the first channel junction of the transistor at the bottom channel interface surface, and the second channel junction of the transistor at the sidewall channel interface surface, the first channel junction and the second channel junction of the respective cavity comprising different channel junction characteristics.

16. The device of claim 14 , wherein the first channel junction comprises a first channel buffer region, and the second channel junction comprises a second channel buffer region.

17. The device of claim 16 , wherein the first channel buffer region and the second channel buffer region are differently-doped channel buffer regions.

18. The device of claim 16 , wherein the first channel buffer region and the second channel buffer region have different thicknesses.

19. The device of claim 16 , wherein the first channel buffer region is thicker than the second channel buffer region and recessed at least partially into the semiconductor material.

Assignees

• Globalfoundries Inc

Inventors

• Tripathi Neeraj
• Prindle Christopher Michael

Classifications

• H10P14/36

  characterised by treatments done before the formation of the materials · CPC title

• H10P14/3242 Primary

  Structure · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/021

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title

• H10D30/60 Primary

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title