V-shaped epitaxially formed semiconductor layer

Patent metadata

Field	Value
Publication number	US-9601574-B2
Application number	US-201414584699-A
Country	US
Kind code	B2
Filing date	Dec 29, 2014
Priority date	Dec 29, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material. The method further includes epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess, and removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature.

First claim

What is claimed is:

1. A method comprising:
forming a recess in a source/drain (S/D) region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material;
epitaxially growing a second semiconductor material, a third semiconductor material, and a fourth semiconductor material within the recess to form a S/D feature in the recess, wherein the fourth semiconductor material is disposed over the third semiconductor material in the recess and the third semiconductor material is disposed over the second semiconductor material in recess, wherein the second semiconductor material includes a dopant at a first concentration, the third semiconductor material includes the dopant at a second concentration, and the fourth semiconductor material includes the dopant at a third concentration, wherein the first concentration is less than the second concentration and the second concentration is greater than the third concentration; and
removing a portion of the S/D feature to form a valley extending into the S/D feature.

2. The method of claim 1 , further comprising forming a silicide feature in the valley.

3. The method of claim 2 , further comprising forming a contact feature on the silicide feature.

4. The method of claim 1 , wherein after removing the portion of the S/D feature to form the valley extending into the S/D feature, the S/D feature includes a first surface aligned in a [111] crystalline orientation and a second surface aligned in the [111] crystalline orientation.

5. The method of claim 4 , wherein the first surface intersects the second surface.

6. The method of claim 1 , wherein the first semiconductor material is different than the second semiconductor material.

7. The method of claim 1 , further comprising forming a gate stack over the semiconductor substrate.

8. The method of claim 1 , wherein removing the portion of the S/D feature to form the valley extending into the S/D feature includes removing a portion of the fourth semiconductor material and a portion of the third semiconductor material.

9. The method of claim 1 , wherein the third concentration is greater than the first concentration.

10. A method comprising:
forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material;
epitaxially growing a second semiconductor material, a third semiconductor material, and a fourth semiconductor material within the recess to form a S/D feature, wherein the fourth semiconductor material is disposed over the third semiconductor material in the recess and the third semiconductor material is disposed over the second semiconductor material in recess, wherein the second semiconductor material includes a dopant at a first concentration, the third semiconductor material includes the dopant at a second concentration, and the fourth semiconductor material includes the dopant at a third concentration, wherein the first concentration is less than the second concentration and the second concentration is greater than the third concentration, wherein the second, third, and fourth semiconductor materials are formed of the same semiconductor material; and
removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature.

11. The method of claim 10 , wherein the second and third semiconductor materials are different than the first semiconductor material.

12. The method of claim 10 , wherein removing the portion of the S/D feature to form the v-shaped valley extending into the S/D feature includes removing a portion of the second semiconductor material and a portion of the third semiconductor material.

13. The method of claim 10 , wherein the v-shaped valley extending into the S/D feature extends through the second semiconductor material and into the third semiconductor material.

14. The method of claim 10 , wherein removing the portion of the S/D feature to form the v-shaped valley extending into the S/D feature includes performing an etch process.

15. A method comprising:
forming a recess in a region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material;
epitaxially growing a second semiconductor material, a third semiconductor material, and a fourth semiconductor material within the recess to form a source/drain feature, wherein the fourth semiconductor material is disposed over the third semiconductor material in the recess and the third semiconductor material is disposed over the second semiconductor material in recess, wherein the second semiconductor material includes a dopant at a first concentration, the third semiconductor material includes the dopant at a second concentration, and the fourth semiconductor material includes the dopant at a third concentration, wherein the first concentration is less than the second concentration and the second concentration is greater than the third concentration; and
removing a portion of the epitaxially grown fourth and third semiconductor materials to form a valley extending into the source/drain feature.

16. The method of claim 15 , further comprising forming a silicide feature in the valley.

17. The method of claim 16 , further comprising forming a contact feature on the silicide feature.

18. The method of claim 15 , wherein after removing the portion of the epitaxially grown second and third semiconductor materials, the valley includes a first surface aligned in a [111] crystalline orientation and a second surface aligned in the [111] crystalline orientation, and
wherein the first surface intersects the second surface.

19. The method of claim 15 , wherein the first, second, and third semiconductor materials are different.

20. The method of claim 15 , wherein removing the portion of the epitaxially grown fourth and third semiconductor materials to form the valley extending into the source/drain feature further includes removing a portion of the second semiconductor material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kwok Tsz-Mei
• Yu Ming-Hua
• Li Chii-Horng

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3408

  Silicon carbide · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H01L29/66636

  Electricity · mapped topic

• H01L29/0847 Primary

  Electricity · mapped topic