System and method for electrical testing of through silicon vias (TSVs)

Patent metadata

Field	Value
Publication number	US-9874598-B2
Application number	US-201514827796-A
Country	US
Kind code	B2
Filing date	Aug 17, 2015
Priority date	Feb 16, 2010
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.

First claim

The invention claimed is:

1. An apparatus comprising:
a first semiconductor substrate layer of a first conductivity type having a first top surface and a first bottom surface;
a first tubular column of insulating material in said first semiconductor substrate layer extending from the first top surface to a depth that does not reach the first bottom surface;
a first metal material disposed within the first tubular column of insulating material, said first metal material having a bottom surface in contact with the first semiconductor substrate layer; and
a second semiconductor substrate layer of a second conductivity type having a second top surface and a second bottom surface, wherein the second bottom surface is in contact with the first top surface, said first tubular column of insulating material and said first metal material disposed within the first tubular column of insulating material extending through the second semiconductor substrate layer.

2. The apparatus of claim 1 , further comprising an integrated transistor device formed in the first top surface and electrically connected to the first metal material disposed within the first tubular column of insulating material.

3. The apparatus of claim 1 , further comprising a third semiconductor substrate layer of the first conductivity type having a third top surface and a third bottom surface, wherein the third bottom surface is in contact with the second top surface, said first tubular column of insulating material and said first metal material disposed within the first tubular column of insulating material extending through the third semiconductor substrate layer.

4. The apparatus of claim 3 , further comprising an integrated transistor device formed in the third top surface and electrically connected to the first metal material disposed within the first tubular column of insulating material.

5. The apparatus of claim 1 , further comprising a testing circuit configured to generate a testing current applied to said first metal material to flow therethrough and into said first semiconductor substrate layer at the bottom surface of the first metal material that is in contact with the first semiconductor substrate layer.

6. The apparatus of claim 1 , wherein the first tubular column has one of a circular, square or rectangular cross-section.

7. An apparatus comprising:
a first semiconductor substrate layer of a first conductivity type having a first top surface and a first bottom surface;
a first tubular column of insulating material in said first semiconductor substrate layer extending from the first top surface to a depth that does not reach the first bottom surface;
a first metal material disposed within the first tubular column of insulating material, said first metal material having a bottom surface in contact with the first semiconductor substrate layer;
a second tubular column of insulating material coaxial with the first tubular column of insulating material and disposed within the first metal material and extending from the first top surface to a depth that does not reach the first bottom surface;
a region of a second conductivity type disposed in the first semiconductor substrate layer of the first conductivity type at a bottom of the second tubular column of insulating material; and
a second metal material disposed within the second tubular column of insulating material, said second metal material having a bottom surface in contact with the region of the second conductivity type.

8. The apparatus of claim 7 , further comprising an integrated transistor device formed in the first top surface and electrically connected to the second metal material disposed within the second tubular column of insulating material.

9. The apparatus of claim 7 , further comprising a testing circuit configured to generate a testing current applied to said first metal material to flow therethrough and into said first semiconductor substrate layer at the bottom surface of the first metal material that is in contact with the first semiconductor substrate layer and flow out from the region of the second conductivity type and through the second metal material.

10. The apparatus of claim 7 , further comprising a testing circuit configured to generate a testing current applied to said first metal material to flow therethrough and into said first semiconductor substrate layer at the bottom surface of the first metal material that is in contact with the first semiconductor substrate layer.

11. The apparatus of claim 7 , wherein the first and second tubular columns have one of a circular, square or rectangular cross-section.

12. The apparatus of claim 7 , further comprising an integrated transistor device formed in the first top surface and electrically connected to the first metal material disposed within the first tubular column of insulating material.

13. An apparatus, comprising:
a first semiconductor substrate layer of a first conductivity type having a first top surface and a first bottom surface;
a first tubular column of insulating material in said first semiconductor substrate layer extending from the first top surface to a first depth that does not reach the first bottom surface;
a second tubular column of insulating material in said first semiconductor substrate layer extending from the first top surface to a second depth that does not reach the first bottom surface;
a region of a second conductivity type disposed in the first semiconductor substrate layer of the first conductivity type at a bottom of the second tubular column of insulating material;
a first metal material disposed within the first tubular column of insulating material, said first metal material having a bottom surface in contact with the first semiconductor substrate layer; and
a second metal material disposed within the second tubular column of insulating material, said second metal material having a bottom surface in contact with the region of the second conductivity type.

14. The apparatus of claim 13 , further comprising an integrated transistor device formed in the first top surface and electrically connected to the second metal material disposed within the second tubular column of insulating material.

15. The apparatus of claim 13 , further comprising integrated circuitry formed in the first top surface and electrically connected to the first and second metal materials.

16. The apparatus of claim 13 , further comprising a second semiconductor substrate layer of a second conductivity type having a second top surface and a second bottom surface, wherein the second bottom surface is in contact with the first top surface, said first and second tubular columns of insulating material extending through the second semiconductor substrate layer.

17. The apparatus of claim 13 , further comprising a third semiconductor substrate layer of the first conductivity type having a third top surface and a third bottom surface, wherein the third bottom surface is in contact with the second top surface, said first and second tubular columns of insulating material extending through the third semiconductor substrate layer.

18. The apparatus of claim 17 , further comprising integrated circuitry formed in the third top surface and electrically connected to the first and second metal materials.

19. The apparatus of claim 13 , further comprising a testing circuit configured to generate a testing current applied to first metal material to flow therethrough and into said first semiconductor substrate layer at the bottom surface of the first metal

Assignees

• St Microelectronics Srl

Inventors

• Pagani Alberto

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2125

  Top-view shapes · CPC title