Crack stopping structure in wafer level packaging (WLP)

Patent metadata

Field	Value
Publication number	US-9379065-B2
Application number	US-201313969436-A
Country	US
Kind code	B2
Filing date	Aug 16, 2013
Priority date	Aug 16, 2013
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the several metal layers, a first metal redistribution layer coupled to the pad, an under bump metallization (UBM) layer coupled to the first metal redistribution layer. The semiconductor device includes several crack stopping structures configured to surround a bump area of the semiconductor device and a pad area of the semiconductor device. The bump area includes the UBM layer. The pad area includes the pad. In some implementations, at least one crack stopping structure includes a first metal layer and a first via. In some implementations, at least one crack stopping structure further includes a second metal layer, a second via, and a third metal layer. In some implementations, at least one crack stopping structure is an inverted pyramid crack stopping structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a plurality of metal layers and dielectric layers coupled to the substrate;
a pad coupled to one of the plurality of metal layers;
a first metal redistribution layer coupled to the pad;
an under bump metallization (UBM) layer coupled to the first metal redistribution layer; and
a plurality of crack stopping structures configured to at least partially surround a portion of the semiconductor device, wherein the portion comprises:
a bump area comprising the UBM layer; and
a pad area comprising the pad,
wherein at least one crack stopping structure comprises a first metal layer and a first via,
wherein at least one crack stopping structure is formed in at least one dielectric layer of the semiconductor device,
wherein at least one crack stopping structure is free of an electrical connection with a circuit element of the semiconductor device, when the semiconductor device is operational.

2. The semiconductor device of claim 1 , wherein the at least one crack stopping structure further includes a second metal layer, a second via, and a third metal layer.

3. The semiconductor device of claim 1 , wherein the at least one crack stopping structure comprises an inverted pyramid crack stopping structure, the inverted pyramid crack stopping structure comprising:
the first metal layer comprising a first length;
the first via coupled to the first metal layer;
a second metal layer coupled to the first via, the second metal layer comprising a second length that is less than the first length; and
a second via coupled to the second metal laver,
wherein the first metal laver, the first via, the second metal laver, and the second via are formed in at least one dielectric layer of the semiconductor device.

4. The semiconductor device of claim 1 , wherein the at least one crack stopping structure completely surrounds the portion comprising the bump area and the pad area, while providing a space for one or more metal interconnects to laterally traverse the at least one crack stopping structure.

5. The semiconductor device of claim 1 , wherein the at least crack stopping structure is configured to stop a crack from propagating in the semiconductor device.

6. The semiconductor device of claim 1 , wherein the semiconductor device is one of at least a die, a die package, an integrated circuit (IC), a wafer, and/or an interposer.

7. The semiconductor device of claim 1 , wherein the semiconductor device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

8. An apparatus comprising:
a substrate;
a plurality of metal layers and dielectric layers coupled to the substrate;
a pad coupled to one of the plurality of metal layers;
a first metal redistribution layer coupled to the pad;
an under bump metallization (UBM) layer coupled to the first metal redistribution layer; and
a means for stopping crack from propagating in the apparatus, the means for stopping crack configured to at least partially surround a portion of the apparatus, wherein the portion comprises:
a bump area comprising the UBM layer; and
a pad area comprising the pad,
wherein the means for stopping crack is formed in at least one dielectric layer of the apparatus,
wherein the means for stopping crack is free of an electrical connection with a circuit element of the apparatus, when the apparatus is operational.

9. The apparatus of claim 1 , wherein the means for stopping crack comprises a first metal layer and a first via.

10. The apparatus of claim 8 , wherein the means for stopping crack further comprises a second metal layer, a second via, and a third metal layer.

11. The apparatus of claim 1 , wherein the means for stopping crack includes an inverted pyramid crack stopping structure, the inverted pyramid crack stopping structure comprising:
a first metal layer comprising a first length;
a first via coupled to the first metal layer;
a second metal layer coupled to the first via, the second metal layer comprising a second length that is less than the first length; and
a second via coupled to the second metal layer,
wherein the first metal layer, the first via, the second metal layer, and the second via are formed in at least one dielectric layer of the apparatus.

12. The apparatus of claim 1 , wherein the means for stopping crack completely surrounds the portion comprising the bump area and the pad area, while providing a space for one or more metal interconnects to laterally traverse the means for stopping crack.

13. The apparatus of claim 1 , wherein the apparatus is one of at least a die, a die package, an integrated circuit (IC), a wafer, and/or an interposer.

14. The apparatus of claim 1 , wherein the apparatus is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

15. An apparatus comprising a semiconductor device, the semiconductor device comprising:
a substrate;
a plurality of metal layers and dielectric layers coupled to the substrate;
a pad coupled to one of the plurality of metal layers;
a first metal redistribution layer coupled to the pad;
an under bump metallization (UBM) layer coupled to the first metal redistribution layer; and
a means for stopping crack from propagating in the semiconductor device, the means for stopping crack configured to at least partially surround a portion of the semiconductor device, wherein the portion comprises:
a bump area comprising the UBM layer; and
a pad area comprising the pad
wherein the means for stopping crack is formed in at least one dielectric layer of the semiconductor device,
wherein the means for stopping crack is free of an electrical connection with a circuit element of the semiconductor device, when the semiconductor device is operational.

16. The semiconductor device of claim 1 , wherein the bump area comprises a first portion of the semiconductor device that is at least partially vertically aligned with the UBM layer.

17. The semiconductor device of claim 1 , wherein the pad area comprises a first portion of the semiconductor device that is at least partially vertically aligned with the pad.

18. The semiconductor device of claim 1 , wherein the plurality of crack stopping structures is configured to at least laterally surround the portion of the semiconductor device.

19. The apparatus of claim 8 , wherein the bump area comprises a first portion of the apparatus that is at least partially vertically aligned with the UBM layer.

20. The apparatus of claim 8 , wherein the pad area comprises a first portion of the apparatus that is at least partially vertically aligned with the pad.

21. The apparatus of claim 8 , wherein the means for stopping crack from propagating in the apparatus is configured to at least laterally surround the portion of the apparatus.

22. The apparatus of claim 11 , wherein a center of the first metal layer, a center of the first via, a center of the second metal layer, and a center of the second via are substantially vertically aligned with each other.

23. Th

Assignees

• Qualcomm Inc

Inventors

• Keser Lizabeth Ann
• Bao Zhongping
• Alvarado Reynante Tamunan

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title