Phase detector, phase-frequency detector, and digital phase locked loop

Patent metadata

Field	Value
Publication number	US-9337849-B2
Application number	US-201414325055-A
Country	US
Kind code	B2
Filing date	Jul 7, 2014
Priority date	Jul 8, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.

First claim

What is claimed is:

1. A phase detector comprising:
a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal;
a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal; and
an initial voltage control circuit configured to variably control an initial voltage of an input terminal of the latch circuit by performing a voltage determining operation based on a control signal.

2. The phase detector according to claim 1 , wherein the latch circuit comprises a first input terminal and a second input terminal, and
wherein the initial voltage control circuit comprises a first voltage control subcircuit which controls the first input terminal and a second voltage control subcircuit which controls the second input terminal.

3. The phase detector according to claim 2 , wherein the first voltage control subcircuit and the second voltage control subcircuit divide a power supply voltage in response to the control signal, and control initial voltages of the first input terminal and the second input terminal, respectively.

4. The phase detector according to claim 2 , wherein the phase comparing circuit first discharges one of the first input terminal and the second input terminal according to the phase difference between the first clock signal and the second clock signal.

5. The phase detector according to claim 1 , further comprising:
an offset controller configured to output the control signal based on an offset control signal and the second clock signal.

6. The phase detector according to claim 5 , wherein the offset controller comprises:
a sigma-delta modulator configured to dither the offset control signal and output a modulation signal according to the second clock signal; and
a decoder configured to decode the modulation signal and output the control signal according to the second clock signal.

7. A digital phase locked loop comprising:
an offset controller configured to dither an offset control signal using a first clock signal and output a control signal;
a phase detector configured to detect a phase difference between the first clock signal and a second clock signal according to the control signal and output a phase detection signal;
a filter configured to filter the phase detection signal;
a digital oscillator configured to generate a third clock signal based on an output of the filter, wherein an initial frequency of the third clock signal is controlled according to an initialization signal; and
a feedback circuit configured to divide the third clock signal and generate the second clock signal.

8. The digital phase locked loop according to claim 7 , wherein the phase detector comprises:
a phase comparing circuit configured to detect and output a phase difference between the first clock signal and the second clock signal;
a latch circuit configured to latch an output signal of the phase comparing circuit and output the phase detection signal; and
an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to the control signal.

9. The digital phase locked loop according to claim 8 , wherein the latch circuit comprises a first input terminal and a second input terminal, and
wherein the initial voltage control circuit comprises a first voltage control subcircuit which controls an initial voltage of the first input terminal and a second voltage control subcircuit which controls an initial voltage of the second input terminal.

10. The digital phase locked loop according to claim 7 , wherein the control signal is synchronous with the second clock signal.

11. The digital phase locked loop according to claim 10 , wherein the offset controller comprises:
a sigma-delta modulator configured to dither the offset control signal and output a modulation signal according to the second clock signal; and
a decoder configured to decode the modulation signal and output the control signal according to the second clock signal.

12. A phase-frequency detector comprising:
a first flip-flop configured to latch a power supply voltage according to a first clock signal and output a first internal clock signal;
a second flip-flop configured to latch the power supply voltage according to a second clock signal and output a second internal clock signal;
a reset circuit configured to logically combine the first internal clock signal and the second internal clock signal and generate a reset signal to reset the first flip-flop and the second flip-flop;
a timing controller configured to generate a third internal clock signal by delaying the first internal clock signal, to generate a fourth internal clock signal by delaying the second internal clock signal and to generate a control signal by logically combining the external control signal where the control signal is aligned with the fourth internal clock signal; and
a phase detector configured to detect a phase difference between the third internal clock signal and the fourth internal clock signal according to the control signal, and output a phase detection signal.

13. The phase-frequency detector according to claim 12 , wherein the phase detector comprises:
a phase comparing circuit configured to detect and output a phase difference between the third internal clock signal and the fourth internal clock signal;
a latch circuit configured to latch an output signal of the phase comparing circuit and output the phase detection signal; and
an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to the control signal.

14. The phase-frequency detector according to claim 13 , wherein the latch circuit comprises a first input terminal and a second input terminal, and
wherein the initial voltage control circuit comprises a first voltage control subcircuit which controls an initial voltage of the first input terminal and a second voltage control subcircuit which controls an initial voltage of the second input terminal.

15. The phase-frequency detector according to claim 13 , wherein the phase comparing circuit first discharges one of the first input terminal and the second input terminal according to the phase difference between the third internal clock signal and the fourth internal clock signal.

16. The phase-frequency detector according to claim 12 , further comprising:
a sigma-delta modulator configured to dither an offset control signal and output the external control signal according to the second clock signal.

Assignees

• Sk Hynix Inc
• Iucf Hyu

Inventors

• Kim Young-Hoon
• Jang Soo-Young
• Yoo Chang-Sik
• Jeong Chun-Seok
• Lee Kang-Seol

Classifications

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title