XOR phase detector, phase-locked loop, and method of operating a PLL

Patent metadata

Field	Value
Publication number	US-9401723-B2
Application number	US-201514709686-A
Country	US
Kind code	B2
Filing date	May 12, 2015
Priority date	Dec 12, 2014
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.

First claim

The invention claimed is:

1. An XOR phase detector for a phase-locked loop PLL, comprising:
an XOR gate which has a first input for receiving a periodic reference signal and a second input connected or connectable to an output of a frequency divider of the PLL, and
a level shifter which has a level shifter input connected to an output of the XOR gate and a level shifter output connected or connectable to a voltage-controlled oscillator VCO of the PLL, wherein the level shifter is connected or connectable between a low voltage provider and a high voltage provider and has associated with it a high level and a low level and is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high,
wherein the level shifter further has a setpoint input for setting the high level to a setpoint level.

2. The XOR phase detector of claim 1 , comprising a memory element for memorizing the setpoint level, wherein the setpoint input of the level shifter is connected to an output of the memory element so as to receive the setpoint level from the memory element.

3. The XOR phase detector of claim 2 , comprising a level shift control unit which comprises said memory element and which is arranged to set the setpoint level in the memory element in an initialization phase.

4. The XOR phase detector of claim 3 , wherein the initialization phase comprises:
locking the PLL at a first level of a tuning voltage Vtune of the VCO;
setting the setpoint level on the basis of or in accordance with said first level of the tuning voltage Vtune of the VCO.

5. The XOR phase detector of claim 4 , wherein said act of setting the setpoint level on the basis of or in accordance with said first level of the tuning voltage Vtune of the VCO comprises:
setting the setpoint level in accordance with a linearly increasing function of the tuning voltage Vtune.

6. The XOR phase detector of claim 3 , wherein the initialization phase comprises:
increasing the setpoint level in response to detecting that the PLL does not lock.

7. The XOR phase detector of claim 6 , wherein the level shift control unit has a sequence of one or more different candidate levels programmed in it and the initialization phase comprises setting the setpoint level to the first candidate level of the sequence and repeating the following cycle, starting with the first candidate level of the sequence and terminating when the PLL has locked or when the set of candidate levels is exhausted:
detecting whether the PLL has locked;
in response to detecting that the PLL has not locked, setting the setpoint level to the next candidate level of the sequence.

8. The XOR phase detector of claim 1 , wherein the level shifter comprises:
a resistor connected between the high voltage provider and the level shifter output; and
a switch connected between the low voltage provider and the level shifter output and having a switch control input which is connected to or acts as the level shifter input.

9. The XOR phase detector of claim 8 , wherein the switch comprises a bipolar junction transistor BJT, the BJT having an emitter connected to the low voltage provider, a collector connected to a low-side terminal of the resistor, and a base connected to the output of the XOR gate, or wherein the switch comprises a metal oxide semiconductor field-effect transistor (MOSFET) having a source connected to the low voltage provider, a drain connected to a low-side terminal of the resistor, and a gate connected to the output of the XOR gate.

10. The XOR phase detector of claim 9 , wherein the level shifter comprises one or more pull-down branches, wherein each of said pull-down branches is connected between the level shifter output and the low voltage provider.

11. The XOR phase detector of claim 10 , wherein each of said pull-down branches comprises a switch and a resistor connected in series, wherein the switch has a switch control input connected to the setpoint input.

12. The XOR phase detector of claim 8 , wherein the level shifter comprises a regulator connected between the resistor and the high voltage provider and arranged to drive the high-side terminal of the resistor to a voltage lower than that of the high voltage provider as a function of the setpoint level.

13. A phase-locked loop PLL, comprising a voltage-controlled oscillator VCO, a frequency divider, an XOR phase detector, and a low-pass filter;
wherein the frequency divider has an input connected to an output of the VCO, the XOR phase detector comprises an XOR gate and a level shifter, the XOR gate has a first input for receiving a periodic reference signal and a second input connected to an output of the frequency divider, the level shifter has a level shifter input connected to an output of the XOR gate, the low-pass filter has an input connected to an output of the XOR phase detector, and the VCO has an input connected to an output of the low-pass filter,
wherein the level shifter is connected or connectable between a low voltage provider and a high voltage provider and has associated with it a high level and a low level and is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR gate is low or high,
wherein the level shifter further has a setpoint input for setting the high level to a setpoint level.

14. A method of operating an XOR phase detector in a phase-locked loop PLL, the PLL comprising a voltage-controlled oscillator VCO, a frequency divider, the XOR phase detector, and a low-pass filter;
wherein the frequency divider has an input connected to an output of the VCO, the XOR phase detector comprises an XOR gate and a level shifter, the XOR gate has a first input receiving a periodic reference signal and a second input connected to an output of the frequency divider, the level shifter has a level shifter input connected to an output of the XOR gate, the low-pass filter has an input connected to an output of the XOR phase detector, and the VCO has an input connected to an output of the low-pass filter,
wherein the level shifter is connected between a low voltage provider and a high voltage provider and has associated with it a high level and a low level and delivers at its output the high level or the low level depending on whether the voltage at the output of the XOR gate is low or high,
wherein the method comprises: varying the high level so as to adapt the high level to an operating frequency of the PLL or to a range of operating frequencies of the PLL.

Assignees

• Montoriol Gilles
• Doare Olivier Vincent
• Goumballa Birama
• Salle Didier
• Freescale Semiconductor Inc

Inventors

• Montoriol Gilles
• Doare Olivier Vincent
• Goumballa Birama
• Salle Didier

Classifications

• H03L7/097 Primary

  using a comparator for comparing the voltages obtained from two frequency to voltage converters · CPC title

• H03L7/095

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/1976 Primary

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title