Method of fabricating a semiconductor device

Patent metadata

Field	Value
Publication number	US-10157766-B2
Application number	US-201415112429-A
Country	US
Kind code	B2
Filing date	Mar 19, 2014
Priority date	Mar 19, 2014
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.

First claim

The invention claimed is:

1. A method of fabricating a semiconductor device, comprising:
sequentially forming a first glue layer and a first release layer on a first substrate;
sequentially forming a second release layer and a second glue layer on a second substrate;
attaching the first substrate to the second substrate in such a way that the first release layer is in contact with the second glue layer;
performing a back-grinding process to reduce a thickness of the second substrate;
forming a conductive pad on the second substrate; and
detaching the first substrate from the second substrate resulting in the second substrate having the second glue layer and second release layer remaining thereon and resulting in the first substrate having the first glue layer remaining thereon.

2. The method of claim 1 , further comprising forming an additional release layer on the first substrate, before the forming of the first glue layer and the first release layer.

3. The method of claim 1 , further comprising cracking the first release layer to detach the first substrate from the second substrate.

4. The method of claim 3 , further comprising sawing the second substrate to form semiconductor chips separated from each other.

5. The method of claim 4 , further comprising:
mounting a first semiconductor chip of the semiconductor chips on a package substrate;
forming a mold layer to cover the first semiconductor chip; and
attaching outer solder balls onto a bottom surface of the package substrate.

6. The method of claim 3 ,
wherein cracking the first release layer to detach the first substrate from the second substrate results in the second substrate having the second glue layer and second release layer remaining thereon, and
wherein the method further comprises detaching the second glue layer from the second release layer and second substrate.

7. The method of claim 6 , wherein the second glue layer is formed directly on the second release layer after the second release layer is formed on the second substrate.

8. The method of claim 1 , further comprising:
mounting first semiconductor chips spaced apart from each other, on the second substrate, each of the first semiconductor chips being in contact with the conductive pad;
forming a mold layer on the second substrate to cover the first semiconductor chips;
cracking the first release layer to detach the first substrate from the second substrate; and
performing a singulation process to cut the mold layer and a portion of the second substrate along regions between the first semiconductor chips, thereby forming semiconductor packages, each of which includes a corresponding one of the first semiconductor chips, a second semiconductor chip provided below the corresponding one of the first semiconductor chips, and a mold layer covering the corresponding one of the first semiconductor chips.

9. The method of claim 8 , further comprising, before the detaching of the first substrate, performing a grinding process to remove a portion of the mold layer.

10. The method of claim 1 , wherein the second substrate comprises a through via, and the back-grinding process is performed to expose the through via.

11. The method of claim 1 , wherein the first and second glue layers and the first and second release layers are formed of thermosetting resins.

12. The method of claim 11 , wherein the first and second release layers are formed to have a content of cross-linking agent that is lower than that of the first and second glue layers.

13. The method of claim 11 , wherein the first and second glue layers and the first and second release layers are formed to have Young's moduli that are lower than those of the first and second substrates.

14. The method of claim 1 , wherein the first glue layer is a thermoplastic resin layer, and the second glue layer and the first and second release layers are thermosetting resin layers.

15. The method of claim 1 , wherein the second substrate further comprises a plurality of conductive bumps provided on a top surface thereof to be in contact with the second release layer.

16. A method of fabricating a semiconductor device, comprising:
sequentially forming a first glue layer and a first release layer on a first substrate;
sequentially forming a second release layer and a second glue layer on a second substrate;
attaching the first substrate to the second substrate in such a way that the first release layer is in contact with the second glue layer; and
performing a back-grinding process to reduce a thickness of the second substrate;
forming a conductive pad on the second substrate,
wherein an adhesive strength between the first glue layer and the second glue layer is lower than adhesive strengths between the first glue layer and the first substrate and between the second glue layer and the second substrate.

17. A method of fabricating a semiconductor device, comprising:
attaching a first substrate to a second substrate using a first glue layer, a first release layer, and a second glue layer that are sequentially interposed between the first and second substrates; and
cracking the first release layer to detach the first substrate from the second substrate,
wherein the method further comprises forming a second release layer between the second glue layer and the second substrate, and
wherein the first release layer, the second glue layer, and the second release layer contain thermosetting resin.

18. The method of claim 17 , wherein the second substrate comprises chip parts and scribe lane parts therebetween, and the method further comprises cutting the scribe lane parts to separate the chip parts from each other.

19. The method of claim 17 ,
wherein cracking the first release layer to detach the first substrate from the second substrate results in the second substrate having the second glue layer and second release layer remaining thereon, and
wherein the method further comprises detaching the second glue layer from the second release layer and second substrate.

Assignees

• Kang Un Byoung
• Sohn Joonsik
• Ahn Jung Seok
• Lee Chungsun
• Cho Taeje
• Samsung Electronics Co Ltd

Inventors

• Kang Un-Byoung
• Sohn Joonsik
• Ahn Jung-Seok
• Lee Chungsun
• Cho Taeje

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10P72/7448

  the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title