Location-specific tuning of stress to control bow to control overlay in semiconductor processing

Patent metadata

Field	Value
Publication number	US-10157747-B2
Application number	US-201715695968-A
Country	US
Kind code	B2
Filing date	Sep 5, 2017
Priority date	Sep 5, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

Techniques herein include systems and methods for correcting pattern overlay errors by correcting or adjusting bowing of wafers. Location-specific tuning of stress on semiconductor substrates reduces overlay error. Location-specific tuning of stress independently modifies specific regions, areas, or point locations on a substrate to change wafer bow at those specific locations, which reduces overlay error on substrates, which in turn improves overlay of subsequent patterns created on the substrate. Techniques herein include receiving a substrate with some amount of overlay error, measuring bow of the substrate to map z-height deviations across the substrate, generating an overlay correction pattern, and then physically modifying internal stresses on the substrate at specific locations with modifications independent of other coordinate locations. Such modifications can include etching a backside surface of the substrate. One or more processing modules can be used for such processing.

First claim

The invention claimed is:

1. A method for correcting wafer overlay, the method comprising:
receiving a substrate having a working surface and a backside surface opposite to the working surface, the substrate having an initial overlay error resulting from one or more micro fabrication processing steps that have been executed to create at least part of a semiconductor device on the working surface of the substrate;
measuring bow of the substrate producing a bow measurement of the substrate that maps z-height deviations on the substrate relative to one or more reference z-height values;
generating an overlay correction pattern that defines adjustments to internal stresses at specific locations on the substrate based on the bow measurement of the substrate, wherein a first given location on the substrate has a different internal stress adjustment defined as compared to a second given location on the substrate in the overlay correction pattern;
coating the backside surface of the substrate with a layer of photoresist;
imaging the layer of photoresist on the backside surface of the substrate using a pattern of actinic radiation based on the overlay correction pattern;
developing the layer of photoresist to remove soluble portions of the layer of photoresist resulting in a relief pattern of photoresist that uncovers portions of the backside surface; and
etching uncovered portions of the backside surface using the relief pattern as an etch mask, the etching resulting in a modified bow of the substrate, the substrate with the modified bow having a second overlay error, the second overlay error having reduced overlay error as compared to the initial overlay error.

2. The method of claim 1 , wherein the backside surface of the substrate includes one or more deposited films having an internal stress that is modifiable when etched.

3. The method of claim 1 , further comprising depositing one or more films on the backside surface of the substrate prior to coating the backside surface with the layer of photoresist.

4. The method of claim 3 , wherein depositing the one or more films on the backside surface includes depositing a first film and depositing a second film, wherein the first film and the second film have opposing stresses.

5. The method of claim 4 , wherein the first film is deposited prior to depositing the second film.

6. The method of claim 3 , wherein depositing the one or more films on the backside surface includes depositing a first film and depositing a second film, wherein the first film has a compressive internal stress, and wherein the second film has a tensile internal stress.

7. The method of claim 1 , wherein the pattern of actinic radiation is projected using a direct-write projection device.

8. The method of claim 7 , wherein the direct-write projection device is configured to project light onto the substrate using one or more micro mirrors or micro gratings.

9. The method of 7 , wherein generating the overlay correction pattern includes defining sufficient portions of an etch mask to remain to define physical support for contact with chucking pins of a substrate holder.

10. The method of claim 1 , wherein steps of receiving the substrate, measuring bow of the substrate, coating the backside, imaging the layer of photoresist, and etching uncovered portions of the backside surface are all executed on a common platform using an automated substrate handling system that transports the substrate among modules for executing overlay error correction of the substrate.

11. The method of claim 1 , wherein the backside surface is coated while the backside surface is facing downward.

12. The method of claim 1 , further comprising removing the relief pattern after etching uncovered portions of the backside surface.

13. The method of claim 1 , wherein the relief pattern is removed using plasma generated at atmospheric pressure.

14. The method of claim 1 , wherein etching uncovered portions of the backside surface includes using a liquid chemistry.

Assignees

• Tokyo Electron Ltd

Inventors

• Devilliers Anton J

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title