Switch circuit and method of switching radio frequency signals

Patent metadata

Field	Value
Publication number	US-10153767-B2
Application number	US-201715656953-A
Country	US
Kind code	B2
Filing date	Jul 21, 2017
Priority date	Oct 10, 2001
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

First claim

What is claimed is:

1. An RF switching circuit comprising:
(a) a switch transistor grouping having a first switch node and a second switch node;
(b) a shunt transistor grouping having a first shunt node coupled with the second switch node and a second shunt node coupled with a reference voltage;
(c) a control logic configured to output a first control signal and a second control signal; and
(d) a negative voltage generator coupled with the control logic, the negative voltage generator being configured to generate a negative power supply voltage with respect to the reference voltage;
wherein:
(i) the switch transistor grouping has a control switch node configured to receive the first control signal;
(ii) the shunt transistor grouping has a control shunt node configured to receive the second control signal; and
(iii) the RF switching circuit is fabricated as a monolithic integrated circuit.

2. The RF switching circuit of claim 1 , wherein the first control signal and the second control signal are each switchable between positive and negative power supplies with respect to the reference voltage.

3. The RF switching circuit of claim 1 , wherein the reference voltage is ground.

4. The RF switching circuit of claim 3 , wherein the negative voltage generator comprises a charge pump.

5. The RF switching circuit of claim 3 , wherein the switch transistor grouping or the shunt transistor grouping comprise a plurality of stacked transistors.

6. The RF switching circuit of claim 3 , wherein the switch transistor grouping or the shunt transistor grouping comprise a plurality of stacked FETs, each of which having a gate that is insulated from its channel.

7. The RF switching circuit of claim 1 , wherein the monolithic integrated circuit is built on a silicon-on-insulator (SOI) substrate.

8. The RF switching circuit of claim 7 , wherein the SOI substrate comprises a thin-film silicon layer.

9. The RF switching circuit of claim 6 , wherein the monolithic integrated circuit is built on a silicon-on-insulator (SOI) substrate.

10. The RF switching circuit of claim 9 , wherein the SOI substrate comprises at least a silicon layer and an insulating layer, wherein sources and drains of the plurality of stacked FETs extend through an entire thickness of the silicon layer and further down to the insulating layer.

11. The RF switching circuit of claim 4 , further comprising:
an oscillator coupled with the charge pump, the charge pump being configured to receive clocking input signals from the oscillator;
a level shifting circuit coupled with the control logic; and
an RF buffer circuit isolating RF signal energy from the charge pump and the control logic.

12. The RF switching circuit of claim 5 , further comprising:
a plurality of switch gate resistors; and
a plurality of shunt gate resistors;
wherein:
the plurality of switch gate resistors couple the control switch node with corresponding gates of the switch transistor grouping; and
the plurality of shunt gate resistors couple the control shunt node with corresponding gates of the shunt transistor grouping.

13. An RF switching circuit comprising:
(a) a switch transistor grouping having a first switch node and a second switch node;
(b) a shunt transistor grouping having a first shunt node coupled with the second switch node and a second shunt node coupled with a reference voltage;
(c) a control logic configured to output a first control signal and a second control signal; and
(d) a negative voltage generator coupled with the control logic, the negative voltage generator being configured to generate a negative power supply voltage with respect to the reference voltage;
wherein:
(i) the switch transistor grouping has a control switch node configured to receive the first control signal; and
(ii) the shunt transistor grouping has a control shunt node configured to receive the second control signal.

14. An on-chip method of switching RF signals comprising:
(a) providing a switch transistor grouping and a shunt transistor grouping;
(b) inputting an RF signal to the switch transistor grouping;
(c) generating a negative voltage with respect to a reference voltage;
(d) generating a first control signal and a second control signal based on the negative voltage;
(e) in an ON state: enabling the switch transistor grouping using the first control signal and disabling the shunt transistor grouping using the second control signal, thereby passing the RF signal; and
(f) in an OFF state: disabling the switch transistor grouping using the first control signal and enabling the shunt transistor grouping using the second control signal, thereby blocking the RF signal from passing.

15. The on-chip method of switching RF signals of claim 14 , wherein (a)-(f) are on a same integrated circuit.

16. The method of claim 15 , wherein the reference voltage is ground.

17. The method of claim 16 , wherein the switch transistor grouping and the shunt transistor grouping comprise FETs.

Assignees

• Psemi Corp

Inventors

• Burgener Mark L
• Cable James S

Classifications

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title

• H03K2017/0803

  against radiation hardening · CPC title

• H03K17/6871 Primary

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03K17/063

  in field-effect transistor switches · CPC title

• H03K17/693

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title