Low power multi-stacked power amplifier

Patent metadata

Field	Value
Publication number	US-9419560-B2
Application number	US-201414286877-A
Country	US
Kind code	B2
Filing date	May 23, 2014
Priority date	May 23, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

An apparatus includes a plurality of stacked transistors in a multi-stacked power amplifier. At least one transistor of the plurality of stacked transistors is configured to operate in a first mode and in a second mode. The at least one transistor of the plurality of stacked transistors is configured to be biased by a low power biasing network to operate in the first mode.

First claim

What is claimed is:

1. An apparatus comprising:
a first biasing network;
a second biasing network;
a plurality of switches coupled to the first biasing network and to the second biasing network; and
a plurality of stacked transistors in a multi-stacked power amplifier, at least one transistor of the plurality of stacked transistors directly coupled to at least one switch of the plurality of switches via a node,
the first biasing network configured to bias the at least one transistor to operate in a first mode and
the second biasing network configured to bias the at least one transistor to operate in a second mode.

2. The apparatus of claim 1 , further comprising:
a first switch of the plurality of switches configured to couple a gate of a first transistor of the plurality of stacked transistors to the first biasing network; and
a second switch of the plurality of switches configured to couple a gate of a second transistor of the plurality of stacked transistors to the first biasing network.

3. The apparatus of claim 2 , further comprising:
a third switch of the plurality of switches configured to couple the gate of the first transistor of the plurality of stacked transistors to the second biasing network; and
a fourth switch of the plurality of switches configured to couple the gate of the second transistor of the plurality of stacked transistors to the second biasing network.

4. The apparatus of claim 1 , wherein the first biasing network comprises a circuit configured to generate a first voltage to cause the at least one transistor to operate in the first mode, and wherein the second biasing network comprises a voltage divider circuit configured to generate a second voltage to cause the at least one transistor to operate in the second mode.

5. The apparatus of claim 1 , further comprising an input matching network coupled to a gate of a first transistor of the plurality of stacked transistors.

6. The apparatus of claim 1 , further comprising an output matching network coupled to an output of a transistor of the plurality of stacked transistors.

7. The apparatus of claim 1 , wherein the first mode corresponds to a linear region of operation, and wherein the second mode corresponds to a saturation region of operation.

8. An apparatus comprising:
means for amplifying an input signal in a multi-stacked power amplifier, the means for amplifying the input signal including a plurality of stacked transistors, at least one transistor of the plurality of stacked transistors configured to operate in a first mode and in a second mode;
first means for generating a first voltage to bias the at least one transistor to operate in the first mode;
second means for generating a second voltage to bias the at least one transistor to operate in the second mode; and
means for switching between the first means for generating the first voltage and the second means for generating the second voltage, the means for switching including a plurality of switches configured to couple the at least one transistor to the first means for generating the first voltage or to the second means for generating the second voltage, the at least one transistor directly coupled to at least one switch of the plurality of switches via a node.

9. The apparatus of claim 8 , wherein the means for switching further comprises:
first means for switching configured to couple a gate of a first transistor of the plurality of stacked transistors to the first means for generating the first voltage; and
second means for switching configured to couple a gate of a second transistor of the plurality of stacked transistors to the first means for generating the first voltage.

10. The apparatus of claim 9 , further comprising:
third means for switching configured to couple the gate of the first transistor of the plurality of stacked transistors to the second means for generating the second voltage; and
fourth means for switching configured to couple the gate of the second transistor of the plurality of stacked transistors to the second means for generating the second voltage.

11. The apparatus of claim 8 , wherein the first means for generating the first voltage comprises a circuit configured to provide the first voltage to a gate of the at least one transistor to cause the at least one transistor to operate in the first mode, and wherein the second means for generating the second voltage comprises a voltage divider circuit configured to provide the second voltage to a gate of the at least one transistor to cause the at least one transistor to operate in the second mode.

12. The apparatus of claim 8 , wherein the first mode corresponds to a linear region of operation, and wherein the second mode corresponds to a saturation region of operation.

13. A method comprising:
receiving a signal to operate a multi-stacked power amplifier at a first power or a second power, the first power less than the second power;
based on the signal indicating the first power, coupling a gate of a transistor of a plurality of stacked transistors of the multi-stacked power amplifier to a first biasing network via a first switch of a plurality of switches that is coupled directly to the transistor via a node to operate the transistor in a first mode; and
based on the signal indicating the second power, coupling the gate of the transistor to a second biasing network via a second switch of the plurality of switches to operate the transistor in a second mode.

14. The method of claim 13 , wherein the first mode corresponds to a linear region of operation of the transistor, and wherein the second mode corresponds to a saturation region of operation of the transistor.

15. The apparatus of claim 1 , further comprising:
a direct current to direct current (DC-DC) converter coupled to a voltage source associated with the plurality of stacked transistors and configured to cause the voltage source to operate at a first voltage corresponding to a first power of the multi-stacked power amplifier or at a second voltage corresponding to a second power of the multi-stacked power amplifier, the first voltage less than the second voltage.

16. The apparatus of claim 1 , wherein the plurality of switches is further configured to respond to a control signal to couple the at least one transistor to the first biasing network to cause the multi-stacked power amplifier to operate at a first power or to the second biasing network to cause the multi-stacked power amplifier to operate at a second power, the first power less than the second power.

17. The apparatus of claim 8 , further comprising means for operating a voltage source associated with the plurality of stacked transistors at a first voltage corresponding to a first power of the multi-stacked power amplifier or at a second voltage corresponding to a second power of the multi-stacked power amplifier, the first voltage less than the second voltage.

18. The apparatus of claim 8 , wherein the means for switching is configured to respond to a control signal to couple the at least one transistor to the first means for generating the first voltage or to the second means for generating the second voltage.

19. The method of claim 13 , further comprising:
based on the signal indicating the first power, coupling, via the first switch of the plurality of switches, the first biasing network to a gate of a first transistor of the plurality of stacked transistors and, via a third switch of the plurality of switches, to a gate of a second transistor of the plurality of stacked transist

Assignees

• Qualcomm Inc

Inventors

• Korol Victor
• Liao Shu-Hsien

Classifications

• H03F3/245

  with semiconductor devices only · CPC title

• H03F1/523

  for amplifiers using field-effect devices (H03F1/526 takes precedence) · CPC title

• H03F1/0272

  by using a signal derived from the output signal · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H03F2200/27

  A biasing circuit node being switched in an amplifier circuit · CPC title