Vertical memory devices having dummy channel regions

Patent metadata

Field	Value
Publication number	US-10153292-B2
Application number	US-201815907667-A
Country	US
Kind code	B2
Filing date	Feb 28, 2018
Priority date	Aug 7, 2015
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

First claim

What is claimed is:

1. A memory device comprising:
a first substrate including a plurality of peripheral circuit devices;
a second substrate on the first substrate;
a plurality of gate electrode layers and a plurality of insulating layers stacked on an upper surface of the second substrate;
a plurality of first channel regions in a first sub-cell array region and a plurality of second channel regions in a second sub-cell array region, each of the first and second channel regions extending in a first direction that is perpendicular to the upper surface of the second substrate to penetrate at least some of the gate electrode layers and insulating layers; and
a separating insulating layer disposed between the first sub-cell array region and the second sub-cell array region, the separating insulating layer extending in a second direction that is parallel to the upper surface of the second substrate,
wherein at least two first channel regions disposed on a first side of the separating insulating layer and at least two second channel regions disposed on a second side of the separating insulating layer are dummy channel regions where no bit line is connected thereto.

2. The memory device of claim 1 , wherein the at least two first channel regions and the at least two second channel regions are offset in the second direction.

3. The memory device of claim 1 , wherein the dummy channel regions directly contact the second substrate.

4. The memory device of claim 1 , wherein the at least two first channel regions are disposed on the first side of the separating insulating layer such that no channel region is positioned between each of the at least two first channel regions and the separating insulating layer.

5. The memory device of claim 1 , wherein the at least two second channel regions are disposed on the second side of the separating insulating layer such that no channel region is positioned between each of the at least two second channel regions and the separating insulating layer.

6. The memory device of claim 1 , wherein the plurality of gate electrode layers extend different lengths in the second direction.

7. The memory device of claim 6 , wherein the separating insulating layer extends in the second direction to an end of at least one of the plurality of gate electrode layers.

8. The memory device of claim 1 , wherein the plurality of peripheral circuit devices are electrically connected to at least a portion of the first and second channel regions and the gate electrode layers.

9. The memory device of claim 1 , wherein the first substrate is a single crystal silicon substrate, and the second substrate is a polycrystalline silicon substrate.

10. The memory device of claim 1 , further comprising a selective epitaxial growth region provided between at least one of the first and second channel regions and the second substrate.

11. The memory device of claim 1 , wherein the dummy channel regions comprise respective annular channel regions that penetrate a lowermost one of the gate electrode layers.

12. The memory device of claim 1 , further comprising a plurality of bit lines wherein the first and second channel regions other than the dummy channel regions are electrically connected to respective ones of the plurality of bit lines.

13. The memory device of claim 1 , further comprising a plurality of polysilicon layers disposed on and directly contacting respective ones of the first and second channel regions, wherein the plurality of polysilicon layers are disposed above the uppermost insulating layers in the first direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong Won
• Lim Seung Hyun
• Kang Chang Seok
• Park Young Woo
• Bae Dae Hoon
• Eun Dong Seog
• Lee Woo Sung
• Lee Jae Duk
• Lim Jae Woo
• Choi Hanmei

Classifications

• H01L27/11524

  Electricity · mapped topic

• H01L27/11529

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic

• H01L29/04

  Electricity · mapped topic