Semiconductor devices

Patent metadata

Field	Value
Publication number	US-9508738-B2
Application number	US-201514591929-A
Country	US
Kind code	B2
Filing date	Jan 8, 2015
Priority date	May 12, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a lower insulation layer;
a plurality of base layer patterns separated from each other on the lower insulation layer;
a separation layer pattern between the base layer patterns;
a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns;
a plurality of gate lines surrounding outer sidewalls of the channels, the gate lines being stacked in the vertical direction and spaced apart from each other; and
a bit line electrically connected to the channels,
wherein the separation layer pattern extends in the same direction as an extending direction of the bit line.

2. The semiconductor device of claim 1 , wherein the base layer patterns include polysilicon or single crystalline silicon.

3. The semiconductor device of claim 2 , wherein the base layer patterns serve as p-type wells.

4. The semiconductor device of claim 1 , wherein the separation layer pattern includes a first separation layer pattern and a second separation layer pattern crossing each other.

5. The semiconductor device of claim 4 , wherein the base layer patterns include island patterns isolated from each other.

6. The semiconductor device of claim 1 , further comprising a peripheral circuit on a substrate,
wherein the lower insulation layer covers the peripheral circuit.

7. The semiconductor device of claim 6 , further comprising:
a first impurity region formed on an upper portion of each of the base layer patterns;
a first connecting contact in contact with the first impurity region;
a second connecting contact electrically connected to the peripheral circuit; and
a connecting wiring for electrically connecting the first connecting contact and the second connecting contact to each other,
wherein the first impurity region, the first connecting contact, the second connecting contact and the connecting wiring are provided for each of the base layer patterns.

8. The semiconductor device of claim 1 , further comprising:
a gate line cut pattern intersecting the gate lines in the vertical direction; and
a second impurity region formed at a portion of the base layer patterns under the gate line cut pattern.

9. The semiconductor device of claim 8 , wherein the gate line cut pattern and the second impurity region extend in a direction crossing the separation layer pattern.

10. The semiconductor device of claim 9 , wherein the second impurity region is cut or separated by the separation layer pattern.

11. The semiconductor device of claim 8 , wherein the gate line cut pattern and the second impurity region extend in the same direction as an extending direction of the separation layer pattern.

12. The semiconductor device of claim 11 , wherein the gate line cut pattern overlaps the separation layer pattern along the vertical direction.

13. The semiconductor device of claim 11 , wherein the second impurity region is formed at a central portion of each of the base layer patterns.

14. A semiconductor device, comprising:
a peripheral circuit on a substrate;
a lower insulation layer covering the peripheral circuit;
a plurality of base layer patterns separated from each other on the lower insulation layer; and
a plurality of cell blocks on the base layer patterns, the cell blocks including:
a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns; and
a plurality of gate lines surrounding outer sidewalls of the channels, the gate lines being stacked in the vertical direction and spaced apart from each other.

15. The semiconductor device of claim 14 , wherein each one of the cell blocks is segmented into a plurality of sub-cell blocks.

16. The semiconductor device of claim 15 , further comprising:
separation layer patterns between the base layer patterns; and
gate line cut patterns between the cell blocks, the gate line cut patterns extending in a direction that crosses the separation layer patterns,
wherein the sub-cell blocks are defined by the separation layer patterns and the gate line cut patterns.

17. The semiconductor device of claim 16 , further comprising a connecting contact electrically connected to the peripheral circuit and provided for each of the sub-cell blocks.

18. A semiconductor device, comprising:
lower transistor on a substrate;
a lower insulation layer; on the substrate, the lower insulation layer covering the lower transitor;
a plurality of base layer patterns separated from each other on the lower insulation layer;
a separation layer pattern between the base layer patterns;
a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns;
a plurality of gate lines surrounding outer sidewalls of the channels, the gate lines being stacked in the vertical direction and spaced apart from each other; and
a first contact extending through the separation layer pattern and the lower insulation layer to be electrically connected to the lower transitor.

19. The semiconductor device of claim 18 , further comprising:
a second contact electrically connected to one of the base layer patterns; and
a connecting wiring electrically connecting the first contact and the second contact to each other.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jae-Duk
• Park Young-Woo

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10P14/27 Primary

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title