Integrated circuit device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10153277-B2
Application number	US-201615390361-A
Country	US
Kind code	B2
Filing date	Dec 23, 2016
Priority date	Feb 1, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction;
a gate electrode layer extending in the gate structure space along the second direction;
a gate insulating layer in the gate structure space and between the substrate and the gate electrode layer; and
an insulating spacer on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer,
wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer, and
wherein the insulating spacer comprises:
a first carbon-containing insulating layer over the pair of width-setting patterns; and
a silicon nitride layer on the pair of width-setting patterns and between the first carbon-containing insulating layer and the pair of width-setting patterns,
wherein the first carbon-containing insulating layer having a first oxygen content, and
wherein the pair of width-setting patterns comprise a second carbon-containing insulating layer having a second oxygen content that is less than the first oxygen content.

2. The integrated circuit device according to claim 1 , wherein the gate electrode layer has a gate length in the first direction that is less than the width of the gate structure space along the first direction.

3. The integrated circuit device according to claim 1 , wherein the gate electrode layer contacts the pair of width-setting patterns.

4. The integrated circuit device according to claim 1 ,
wherein the first carbon-containing insulating layer has a first carbon content, and
wherein the second carbon-containing insulating layer is spaced apart from the first carbon-containing insulating layer and has a second carbon content that is greater than the first carbon content.

5. The integrated circuit device according to claim 1 ,
wherein the first carbon-containing insulating layer has a first carbon content selected from a range of 5 atom % to 15 atom %, and
wherein the second carbon-containing insulating layer has a second carbon content selected from a range of 10 atom % to 25 atom % and is greater than the first carbon content.

6. The integrated circuit device according to claim 1 , wherein at least one of the pair of width-setting patterns comprises a horizontally-extending portion facing a bottom surface of the insulating spacer.

7. The integrated circuit device according to claim 1 , wherein at least one of the pair of width-setting patterns comprises:
a horizontally-extending portion facing a bottom surface of the insulating spacer; and
a vertically-extending portion facing one of opposing sidewalls of the gate electrode layer.

8. The integrated circuit device according to claim 1 , wherein the pair of width-setting patterns have a carbon content selected from a range of 10 atom % to 25 atom % and comprise a SiOCN layer, a SiCN layer, or combinations thereof.

9. An integrated circuit device comprising:
a fin-type active region protruding from a substrate and extending in a first direction;
a device isolation layer covering a lower sidewall of the fin-type active region;
a pair of width-setting patterns on the fin-type active region and the device isolation layer, the pair of width-setting patterns defining a width of a gate structure space in the first direction and extending in a second direction intersecting with the first direction;
a gate electrode layer covering a top surface and both sidewalls of the fin-type active region and extending in the gate structure space along the second direction;
a gate insulating layer in the gate structure space and between the fin-type active region and the gate electrode layer; and
an insulating spacer on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer,
wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer, and
wherein the insulating spacer comprises:
a first carbon-containing insulating layer over the pair of width-setting patterns; and
a silicon nitride layer on the pair of width-setting patterns and between the first carbon-containing insulating layer and the pair of width-setting patterns,
wherein the first carbon-containing insulating layer having a first oxygen content, and
wherein the pair of width-setting patterns comprise a second carbon-containing insulating layer having a second oxygen content that is less than the first oxygen content.

10. The integrated circuit device according to claim 9 ,
wherein the first carbon-containing insulating layer has a first carbon content selected from a range of 5 atom % to 15 atom %, and
wherein the second carbon-containing insulating layer has a second carbon content selected from a range of 10 atom % to 25 atom % and is greater than the first carbon content.

11. The integrated circuit device according to claim 9 , wherein at least one of the pair of width-setting patterns comprises a horizontally-extending portion in the first direction, and
the insulating spacer is spaced apart from the fin-type active region, with the horizontally-extending portion being interposed between the insulating spacer and the fin-type active region.

12. The integrated circuit device according to claim 9 , wherein the insulating spacer is spaced apart from the fin-type active region, with the pair of width-setting patterns being interposed between the insulating spacer and the fin-type active region, the silicon nitride layer faces one of opposing sidewalls of the gate electrode layer, and the first carbon-containing insulating layer covers the silicon nitride layer.

13. The integrated circuit device according to claim 1 , wherein the first carbon-containing insulating layer includes a SiOCN layer having the first oxygen content selected from a range of about 25 atom % to about 50 atom %, and the second carbon-containing insulating layer constituting the pair of width-setting patterns includes a SiOCN layer, a SiCN layer, or combinations thereof.

14. The integrated circuit device according to claim 9 , wherein the first carbon-containing insulating layer includes a SiOCN layer having the first oxygen content selected from a range of about 25 atom % to about 50 atom %, and the second carbon-containing insulating layer constituting the pair of width-setting patterns includes a SiOCN layer, a SiCN layer, or combinations thereof.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Tak Yong-Suk
• Lee Tae-Jong
• Park Gi-Gwan
• Lee Ji-Myoung

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H01L21/823468

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/0665

  Electricity · mapped topic

• H01L21/823437

  Electricity · mapped topic