Non-planar field effect transistor having a semiconductor fin and method for manufacturing

Patent metadata

Field	Value
Publication number	US-9136356-B2
Application number	US-201414176873-A
Country	US
Kind code	B2
Filing date	Feb 10, 2014
Priority date	Feb 10, 2014
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a fin structure over the substrate;
two isolation structures over the substrate, the fin structure between the two isolation structures, wherein each of the two isolation structures has a recess portion and two slope portions adjacent both sides of the recess portion, the recess portions configured to expose portions of both sides of the fin structure;
a gate across the fin structure, and over the fin st…

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chien-Chih
• Hong Long-Jie
• Wang Chih-Lin
• Chang Chia-Der

Classifications

• H10P95/064

  Electricity · mapped topic

• H10P50/73

  Electricity · mapped topic

• H10P50/28

  Electricity · mapped topic

• H10D30/024 Primary

  Electricity · mapped topic

• H10D30/62 Primary

  Electricity · mapped topic