Method for semiconductor device structure
US-12154970-B2 · Nov 26, 2024 · US
US8928048B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928048-B2 |
| Application number | US-201313743454-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 17, 2013 |
| Priority date | Jan 17, 2013 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.
Opening claim text (preview).
What is claimed: 1. A method of forming a transistor, comprising: forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers; removing a portion of said sidewall spacers to define recessed sidewall spacers; removing a portion of said final gate structure to define a recessed final gate structure; performing a conformal deposition process to form a conformal etch stop layer on at least said recessed sidewall spacers and said recessed final g…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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