Methods of forming semiconductor device with self-aligned contact elements and the resulting device

US8928048B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8928048-B2
Application numberUS-201313743454-A
CountryUS
Kind codeB2
Filing dateJan 17, 2013
Priority dateJan 17, 2013
Publication dateJan 6, 2015
Grant dateJan 6, 2015

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  2. Abstract

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Abstract

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One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.

First claim

Opening claim text (preview).

What is claimed: 1. A method of forming a transistor, comprising: forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers; removing a portion of said sidewall spacers to define recessed sidewall spacers; removing a portion of said final gate structure to define a recessed final gate structure; performing a conformal deposition process to form a conformal etch stop layer on at least said recessed sidewall spacers and said recessed final g…

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What does patent US8928048B2 cover?
One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A tran…
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10D64/015. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).