Method of manufacturing a FET using a two dimensional transition metal dichalcogenide including a low power oxygen plasma treatment

Patent metadata

Field	Value
Publication number	US-10147603-B2
Application number	US-201615197004-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	Jun 29, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

In a method of fabricating a field effect transistor, a Mo layer is formed on the substrate. The Mo layer is sulfurized to convert it into a MoS 2 layer. Source and drain electrodes are formed on the MoS 2 layer. The MoS 2 layer is treated with low-power oxygen plasma. A gate dielectric layer is formed on the MoS 2 layer. A gate electrode is formed on the gate dielectric layer. An input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.

First claim

What is claimed is:

1. A method of fabricating a field effect transistor, comprising:
forming a transition metal dichalcogenide (TMD) layer on a substrate; and
treating the TMD layer with low-power oxygen plasma to reduce defects in the TMD layer by forming metal-oxygen bonds, wherein the low-powered oxygen plasma treating causes an increase in electron concentrations in the TMD layer and an increased field-effect mobility values in the TMD layer,
wherein an input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 35 W.

2. The method of claim 1 , wherein the TMD layer includes at least one of MoS 2 and WS 2 .

3. The method of claim 1 , wherein the TMD layer includes MoS 2 .

4. The method of claim 3 , wherein the forming the MoS 2 layer includes:
forming a Mo layer on the substrate; and
sulfurizing the Mo layer, thereby converting the Mo layer into the MoS 2 layer.

5. The method of claim 4 , wherein in the sulfurizing the Mo layer, the substrate is heated at a temperature in a range from 700° C. to 900° C.

6. The method of claim 3 , wherein the input electric power in the low-power oxygen plasma treatment is in a range from 20 W to 35 W.

7. The method of claim 3 , wherein the low-power oxygen plasma treatment is performed for 1 sec to 20 sec.

8. The method of claim 3 , wherein the low-power oxygen plasma treatment is performed for 3 sec to 10 sec.

9. The method of claim 6 , wherein in the low-power oxygen plasma treatment, a DC bias in a range from 20 V to 40 V is applied to the substrate.

10. A method of fabricating a field effect transistor, comprising:
forming a MoS 2 layer on a first substrate;
forming a gate dielectric layer on a second conductive substrate;
forming source and drain electrodes on the gate dielectric layer;
detaching the MoS 2 layer from the first substrate and attaching the detached MoS 2 layer on the gate dielectric layer and the source and drain electrodes; and
treating the MoS 2 layer with low-power oxygen plasma,
wherein an input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.

11. The method of claim 10 , wherein an input electric power in the low-power oxygen plasma treatment is in a range from 20 W to 35 W.

12. The method of claim 10 , wherein the low-power oxygen plasma treatment is performed for 1 sec to 20 sec.

13. The method of claim 10 , wherein the low-power oxygen plasma treatment is performed for 3 sec to 10 sec.

14. The method of claim 10 , wherein in the low-power oxygen plasma treatment, a DC bias in a range from 20 V to 40 V is applied to the substrate.

15. The method of claim 10 , wherein the source and drain electrodes include at least one of Au, Ag and Ti.

16. A method of fabricating a field effect transistor, comprising:
forming a Mo layer on a substrate;
sulfurizing the Mo layer into a MoS 2 layer;
forming source and drain electrodes on the MoS 2 layer;
treating the MoS 2 layer with low-power oxygen plasma;
forming a gate dielectric layer on the MoS 2 layer; and
forming a gate electrode on the gate dielectric layer,
wherein an input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.

17. The method of claim 16 , wherein an input electric power in the low-power oxygen plasma treatment is in a range from 20 W to 35 W.

18. The method of claim 16 , the low-power oxygen plasma treatment is performed after the source and drain electrodes are formed and before the gate dielectric layer is formed.

19. The method of claim 16 , wherein the low-power oxygen plasma treatment is performed for 1 sec to 20 sec.

20. The method of claim 16 , wherein in the sulfurizing the Mo layer, the substrate is heated at a temperature in a range from 700° C. to 900° C.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Lin Shih-Yen
• Liu Chi-Wen
• Lee Si-Chen
• Wu Chong-Rong
• Chen Kuan-Chao

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/3822

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P14/203

  using transformation of metal, e.g. oxidation or nitridation · CPC title

• H10P14/3436 Primary

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title