Systems and methods for assembling two-dimensional materials

US2016240692A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016240692-A1
Application numberUS-201615016933-A
CountryUS
Kind codeA1
Filing dateFeb 5, 2016
Priority dateAug 9, 2013
Publication dateAug 18, 2016
Grant date

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Abstract

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Heterostructures can include multilevel stacks with an electrical contact on a one-dimensional edge of a two-dimensional active layer. A multilevel stack can be provided having a first two-dimensional layer encapsulated between a second layer and a third layer. A first edge of the first two-dimensional layer can be exposed by etching. A metal can be deposited on the edge of the first two-dimensional layer to form an electrical contact.

First claim

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1 . A method for connecting an electrical contact to a two-dimensional layer along a one-dimensional edge thereof comprising: providing a multilevel stack comprising a first two-dimensional layer encapsulated between a second layer and a third layer; exposing an edge of the first two-dimensional layer; and depositing a metal on the edge of the first two-dimensional layer. 2 . The method of claim 1 , wherein the first two-dimensional layer comprises graphene. 3 . The method of claim 1 , wherein the second layer and the third layer comprise hexagonal boron nitride. 4 . The method of claim 1 , wherein the providing comprises encapsulating the first two-dimensional layer between the second layer and the third layer. 5 . The method of claim 4 , wherein the encapsulating comprises: disposing a material forming the second layer onto a polymer layer; stamping a material forming the first two-dimensional layer onto the material forming the second layer; and stamping a material forming the third layer onto the material forming the first two-dimensional layer. 6 . The method of claim 5 , wherein the disposing comprises exfoliating. 7 . The method of claim 5 , wherein the disposing comprises stamping. 8 . The method of claim 5 , wherein the polymer layer comprises a polymer thin film. 9 . The method of claim 5 , wherein stamping the material forming the first layer comprises: disposing the material forming the first layer onto a substrate; and contacting the material forming the first layer with the material forming the second layer. 10 . The method of claim 9 , wherein the disposing the material forming the first layer onto a substrate comprises exfoliating a flake of the material forming the first layer onto the substrate. 11 . The method of claim 9 , wherein the disposing the material forming the first layer onto a substrate comprises chemical vapor deposition. 12 . The method of claim 5 , further comprising stamping alternating flakes of the material forming the first two-dimensional layer and flakes of the material forming the third layer to add additional layers to the multilevel stack. 13 . The method of claim 1 , wherein the exposing the edge of the first two-dimensional layer comprises etching. 14 . The method of claim 13 , wherein the etching comprises plasma-etching. 15 . The method of claim 13 , further comprising: defining a mask on the second layer prior to etching; and etching regions of the multilevel stack outside of the mask. 16 . The method of claim 15 , wherein the defining the mask comprises electron-beam lithography of a resist. 17 . The method of claim 1 , wherein the depositing comprises electron-beam evaporation. 18 . The method of claim 1 , wherein the depositing comprises thermal evaporation. 19 . The method of claim 1 , wherein the metal comprises chromium. 20 . The method of claim 1 , wherein the metal comprises at least one metal selected from a group consisting of palladium, gold, titanium, nickel, aluminum, and niobium. 21 . The method of claim 1 , wherein the heterostructure comprising the deposited metal has a contact resistance of less than about 150 Ω·μm. 22 . The method of claim 1 , wherein the heterostructure comprising the deposited metal has a room-temperature mobility of at least about 140,000 cm 2 /Vs. 23 . The method of claim 1 , wherein the heterostructure comprising the deposited metal has a sheet resistivity of less than about 40 Ω/square at n>4×10 12 cm −2 . 24 . A heterostructure manufactured by a process comprising: providing a multilevel stack comprising a first two-dimensional layer encapsulated between a second layer and a third layer; exposing an edge of the first two-dimensional layer; and depositing a metal on the edge of the first two-dimensional layer. 25 . The heterostructure of claim 24 , wherein the first two-dimensional layer comprises graphene. 26 . The heterostructure of claim 24 , wherein the second layer and the third layer comprise hexagonal boron nitride. 27 . The heterostructure of claim 24 , wherein the providing comprises encapsulating the first two-dimensional layer between the second layer and the third layer. 28 . The heterostructure of claim 27 , wherein the encapsulating comprises: disposing a material forming the second layer onto a polymer layer; stamping a material forming the first two-dimensional layer onto the material forming the second layer; and stamping a material forming the third layer onto the material forming the first two-dimensional layer. 29 . The heterostructure of claim 28 , further comprising stamping alternating flakes of the material forming the first two-dimensional layer and flakes of the material forming the third layer to add additional layers to the multilevel stack. 30 . The heterostructure of claim 24 , wherein the exposing the edge of the first two-dimensional layer comprises etching. 31 . The heterostructure of claim 30 , wherein the etching comprises plasma-etching. 32 . The heterostructure of claim 30 , further comprising: defining a mask on the second layer prior to etching; and etching regions of the multilevel stack outside of the mask. 33 . The heterostructure of claim 32 , wherein defining the mask comprises electron-beam lithography of a resist. 34 . The heterostructure of claim 24 , wherein the depositing comprises electron-beam evaporation. 35 . The heterostructure of claim 24 , wherein the metal comprises chromium. 36 . The heterostructure of claim 24 , wherein the heterostructure has a contact resistance of less than about 150 Ω·μm. 37 . The heterostructure of claim 24 , wherein the heterostructure has a room-temperature mobility of at least about 140,000 cm 2 /Vs. 38 . The heterostructure of claim 24 , wherein the heterostructure has a sheet resistivity of less than about 40 Ω/square at n>4×10 12 cm −2 . 39 . A heterostructure comprising: a first two-dimensional layer comprising an electrical contact disposed on a one-dimensional edge thereof; a second layer; and a third layer, wherein the first two-dimensional layer is disposed between the second layer and the third layer. 40 . The heterostructure of claim 39 , wherein the first two-dimensional layer comprises graphene. 41 . The heterostructure of claim 39 , wherein the second layer and the third layer comprise hexagonal boron nitride. 42 . The heterostructure of claim 39 , wherein the electrical contact comprises chromium. 43 . The heterostructure of claim 39 , wherein the heterostructure has a contact resistance of less than about 150 Ω·μm. 44 . The heterostructure of claim 39 , wherein the heterostructure has a room-temperature mobility of at least about 140,000 cm 2 /Vs. 45 . The heterostructure of claim 39 , wherein the heterostructure has a sheet resistivity of less than about 40 Ω/square at n>4×10 12 cm −2 .

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What does patent US2016240692A1 cover?
Heterostructures can include multilevel stacks with an electrical contact on a one-dimensional edge of a two-dimensional active layer. A multilevel stack can be provided having a first two-dimensional layer encapsulated between a second layer and a third layer. A first edge of the first two-dimensional layer can be exposed by etching. A metal can be deposited on the edge of the first two-dimens…
Who is the assignee on this patent?
Univ Columbia
What technology area does this patent fall under?
Primary CPC classification H10D64/62. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Aug 18 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).