Method for fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-10134867-B2
Application number	US-201815947356-A
Country	US
Kind code	B2
Filing date	Apr 6, 2018
Priority date	Aug 29, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A method for manufacturing semiconductor device includes depositing a contact metal layer over a III-V compound layer. An anti-reflective coating (ARC) layer is deposited over the contact metal layer, and an etch stop layer is deposited over the ARC layer. The etch stop layer, the ARC layer, and the contact metal layer are etched to form a contact stack over the III-V compound layer. A conductive layer is deposited over the III-V compound layer, and the conductive layer is etched to form a gate field plate. The etch stop layer has an etch selectivity different from that of the conductive layer.

First claim

What is claimed is:

1. A method comprising:
depositing a contact metal layer over a III-V compound layer;
depositing an anti-reflective coating (ARC) layer over the contact metal layer;
depositing an etch stop layer over the ARC layer;
etching the etch stop layer, the ARC layer, and the contact metal layer to form a contact stack over the III-V compound layer;
depositing a conductive layer over the III-V compound layer; and
etching the conductive layer to form a gate field plate, wherein the etch stop layer has an etch selectivity different from that of the conductive layer.

2. The method of claim 1 , wherein the conductive layer and the ARC layer comprises the same material.

3. The method of claim 1 , wherein etching the conductive layer is performed such that the etch stop layer is substantially free from coverage by the gate field plate.

4. The method of claim 1 , further comprising:
etching the etch stop layer to expose the ARC layer; and
forming a source/drain electrode over the ARC layer.

5. The method of claim 4 , wherein etching the etch stop layer is performed such that a portion of the etch stop layer remains over the ARC layer after etching the etch stop layer.

6. The method of claim 1 , wherein etching the conductive layer is performed such that a top of the gate field plate is in a position lower than a bottom of the ARC layer.

7. The method of claim 1 , wherein depositing the etch stop layer is performed such that the etch stop layer is in contact with the ARC layer.

8. The method of claim 1 , further comprising:
depositing a dielectric layer over the gate field plate and the contact stack.

9. The method of claim 8 , further comprising:
etching the dielectric layer to form a hole in the dielectric layer; and
forming a gate in the hole and over the III-V compound layer.

10. The method of claim 9 , wherein forming the gate is performed such that a top of the gate is in a position higher than a top of the gate field plate.

11. The method of claim 1 , wherein the ARC layer comprises metal.

12. A method comprising:
epitaxially growing a second III-V compound layer over a first III-V compound layer;
depositing a contact metal layer over the second III-V compound layer;
depositing an anti-reflective coating (ARC) layer over the contact metal layer;
depositing a protective layer over the ARC layer;
etching the protective layer, the ARC layer, and the contact metal layer to define a contact stack over the second III-V compound layer;
depositing a conductive layer over the second III-V compound layer, wherein the conductive layer and the ARC layer comprises the same material; and
etching the conductive layer to define a gate field plate.

13. The method of claim 12 , wherein etching the conductive layer is performed such that the gate field plate is separated from the protective layer.

14. The method of claim 12 , further comprising:
forming a gate over the second III-V compound layer after etching the conductive layer.

15. A method comprising:
epitaxially growing a second III-V compound layer over a first III-V compound layer;
depositing a contact metal layer over the second III-V compound layer;
depositing an anti-reflective coating (ARC) layer over the contact metal layer;
depositing an etch stop layer over the ARC layer;
etching the etch stop layer, the ARC layer, and the contact metal layer to form two separate contact stacks over the second III-V compound layer;
depositing a dielectric layer over the two separate contact stacks;
removing a portion of the dielectric layer and a portion of the etch stop layer to expose the ARC layer; and
forming source/drain electrodes over the two separate contact stacks.

16. The method of claim 15 , wherein etching the etch stop layer, the ARC layer, and the contact metal layer is performed such that the ARC layer is separated into two separate portions.

17. The method of claim 15 , further comprising:
depositing a conductive layer over the second III-V compound layer; and
etching the conductive layer to form a gate field plate.

18. The method of claim 17 , wherein etching the conductive layer is stopped at the etch stop layer.

19. The method of claim 17 , further comprising:
forming a gate over the second III-V compound layer, wherein forming the gate is performed such that the gate is substantially free from coverage by the gate field plate.

20. The method of claim 17 , wherein etching the conductive layer is performed such that a top of the gate field plate is in a position lower than a top of the contact metal layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• You Jheng-Sheng
• Lin Hsin-Chih
• Huang Kun-Ming
• Chen Lieh-Chuan
• Chu Po-Tao
• Wang Shen-Ping
• Kuo Chien-Li

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H01L29/402

  Electricity · mapped topic

• H01L29/7786

  Electricity · mapped topic