Non-volatile memory device

Patent metadata

Field	Value
Publication number	US-10128267-B2
Application number	US-201715661401-A
Country	US
Kind code	B2
Filing date	Jul 27, 2017
Priority date	Dec 20, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A non-volatile memory device includes channel hole structures, bit lines, and intermediate wiring. The channel hole structures are arranged in a two-dimensional pattern on and extend vertically from a substrate. The bit lines extend in a first direction, are spaced apart from each other in a second direction crossing the first direction, and are electrically connected to the plurality of channel hole structures. The intermediate wiring which connects channel hole structures and the bit lines. The bit lines includes a first bit line and a second bit line directly connected to the channel hole structures through a first contact and spaced apart in the second direction. The intermediate wiring is between the first bit line and the second bit line.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a plurality of channel hole structures arranged in a two-dimensional pattern on and extending vertically from a substrate;
a plurality of bit lines extending in a first direction, spaced apart from each other in a second direction crossing the first direction, and electrically connected to the plurality of channel hole structures; and
an intemiediate wiring which connects channel hole structures in the first direction among the plurality of channel hole structures and the plurality of bit lines, wherein the plurality of bit lines includes a first bit line and a second bit line directly connected to the channel hole structures through a first contact and spaced apart in the second direction, and wherein the intermediate wiring is between the first bit line and the second bit line and is connected to a third bit line through a second contact having a different structure from the first contact.

2. The non-volatile memory device as claimed in claim 1 , further comprising an intermediate contact which contacts the plurality of channel hole structures and connects the plurality of bit lines or the intermediate wiring and the plurality of channel hole structures.

3. The non-volatile memory device as claimed in claim 2 , further comprising a contact on the intermediate contact and connecting the intermediate contact and one of the plurality of bit lines.

4. The non-volatile memory device as claimed in claim 1 , wherein the first contact and the second contact are at a same level.

5. The non-volatile memory device as claimed in claim 3 , further comprising a first interlayer insulating film and a second interlayer insulating film which are sequentially stacked on the plurality of channel hole structures.

6. The non-volatile memory device as claimed in claim 5 , wherein:
the first contact passes through the second interlayer insulating film, and
the second contact passes through the first and second interlayer insulating films.

7. The non-volatile memory device as claimed in claim 1 , wherein the plurality of channel hole structures connected by the intermediate wiring include at least two channel hole structures which are nearest to each other in the first direction.

8. The non-volatile memory device as claimed in claim 1 , wherein a line pitch between the first bit line and the second bit line is less than a critical dimension of an exposure apparatus.

9. The non-volatile memory device as claimed in claim 8 , wherein the intermediate wiring extends linearly along the first direction.

10. The non-volatile memory device as claimed in claim 1 , wherein the bit line connects at least two channel hole structures of the plurality of channel hole structures which are nearest to each other in the first direction.

11. The non-volatile memory device as claimed in claim 1 , further comprising:
a plurality of gate electrodes and insulating films on the substrate,
wherein the plurality of gate electrodes and the insulating films surround the plurality of channel hole structures and are alternately stacked on the substrate.

12. A non-volatile memory device, comprising:
a plurality of intermediate contacts arranged in a two-dimensional pattern on and connected to a lower film;
a plurality of bit lines on the plurality of intermediate contacts and directly connected to the intermediate contacts arranged along a first direction; and
a plurality of intermediate wirings connecting at least a pair of intermediate contacts between bit lines connected to a plurality of intermediate contacts among the plurality of bit lines and disposed along a first direction among the plurality of intermediate contacts, and the bit lines which are not connected to the intermediate contacts, wherein the intermediate contacts include:
a first intermediate contact directly connected to the bit line, and
a second intermediate contact connected to the bit lines through the bit lines and the intermediate wirings, and
the first intermediate contact and the second intermediate contact are in a matrix form which alternates in a second direction orthogonal to the first direction.

13. The non-volatile memory device as claimed in claim 12 , further comprising:
a substrate in the lower film; and
channel hole structures arranged in a two-dimensional pattern on the substrate and extending perpendicularly from the substrate.

14. The non-volatile memory device as claimed in claim 13 , wherein the channel hole structures are aligned perpendicularly to the intermediate contacts.

15. The non-volatile memory device as claimed in claim 12 , further comprising:
a first contact which connects the first intermediate contact to the bit line, and
a second contact which connects the intermediate wiring to the bit line.

16. A non-volatile memory device, comprising:
channel hole structures;
bit lines connected to the channel hole structures; and
an intermediate wiring connecting the channel hole structures and the bit lines,
wherein the bit lines include a first bit line and a second bit line directly connected to the channel hole structures through a first contact and wherein the intermediate wiring is between the first bit line and the second bit line and is connected to a third bit line through a second contact having a different structure from the first contact.

17. The non-volatile memory device as claimed in claim 16 , further comprising an intermediate contact which contacts the channel hole structures.

18. The non-volatile memory device as claimed in claim 16 , further comprising a contact on the intermediate contact and connecting the intermediate contact and one or more of the bit lines.

19. The non-volatile memory device as claimed in claim 16 , wherein the first contact and the second contact are at a same level.

20. The non-volatile memory device as claimed in claim 16 , further comprising a first interlayer insulating film and a second interlayer insulating film which are sequentially stacked on the channel hole structures.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Sim Woo Joo
• Shin Wang Ho
• Han Kyu Bin

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H10D30/798

  being provided in or under the channel regions · CPC title

• H10D62/213

  Channel regions of field-effect devices · CPC title