Method of manufacturing semiconductor device and semiconductor device

Patent metadata

Field	Value
Publication number	US-2016268286-A1
Application number	US-201514729209-A
Country	US
Kind code	A1
Filing date	Jun 3, 2015
Priority date	Mar 11, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

According to one embodiment of a method of manufacturing a semiconductor device, a film stack in which a first film and a second film are alternately and repeatedly stacked is formed on a semiconductor substrate. Further, silicon oxide which is a first interlayer insulation film is formed at a non-stack area where the film stack is not disposed up to a predetermined height. Furthermore, a silicon compound film including at least one of nitride, carbon, and boron is embedded as a second interlayer insulation film in a recessed portion inside the non-stack area. Additionally, dry etching processing is simultaneously applied to the film stack, and the first and second interlayer insulation films by using a fluorocarbon-based gas.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
forming, on a semiconductor substrate, a film stack where a first film and a second film are alternately and repeatedly stacked; forming silicon oxide, which is a first interlayer insulation film, on a non-stack area where the film stack is not disposed up to a predetermined height; providing a recessed portion in an area having a film thickness of the silicon oxide larger than a predetermined value within the non-stack area; embedding, in the recessed portion, a silicon compound film including at least one of nitride, carbon, and boron as a second interlayer insulation film; simultaneously applying dry etching processing to the film stack and the first and second interlayer insulation films by using a fluorocarbon-based gas; and forming a groove pattern to segment the film stack, and the first and second interlayer insulation films.

2 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the silicon compound film has a thickness corresponding to a film thickness of the silicon oxide at each position inside the non-stack area.

3 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the recessed portion has a depth corresponding to a height of a step on the semiconductor substrate at each position inside the non-stack area.

4 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the dry etching processing is executed after flattening the first and second interlayer insulation films.

5 . The method of manufacturing a semiconductor device according to claim 1 , wherein
a third interlayer insulation film is stacked on an upper side of the silicon compound film, and the third interlayer insulation film is embedded on an upper side of the recessed portion.

6 . The method of manufacturing a semiconductor device according to claim 5 , wherein
the dry etching processing is executed after flattening the first to third interlayer insulation films.

7 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the first film is a SiO film, and the second film is a SiN film.

8 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the silicon compound film is a SiN film, a SiON film, a SiC film, or a SiBN film.

9 . The method of manufacturing a semiconductor device according to claim 5 , wherein
the third interlayer insulation film is a SiO film, a SiN film, a SiON film, a SiC film, or a SiBN film.

10 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the recessed portion has a depth deeper than 300 nm.

11 . A semiconductor device comprising:
a film stack where memory cells are three-dimensionally disposed on a semiconductor substrate; silicon oxide, which is a first interlayer insulation film formed in a non-stack area where the film stack is not disposed up to a predetermined height; a silicon compound film as a second interlayer insulation film configured to be embedded in a recessed portion provided in an area having a film thickness of the silicon oxide larger than a predetermined value within the non-stack area, and further the silicon compound film including at least one of nitride, carbon, and boron; and an isolating portion configured to segment the film stack, and the first and second interlayer insulation films.

12 . The semiconductor device according to claim 11 , wherein
the silicon compound film has a thickness corresponding to a film thickness of the silicon oxide at each position inside the non-stack area.

13 . The semiconductor device according to claim 11 , wherein
the recessed portion has a depth corresponding to a height of a step on the semiconductor substrate at each position inside the non-stack area.

14 . The semiconductor device according to claim 11 , wherein
the first and second interlayer insulation films are flattened.

15 . The semiconductor device according to claim 11 , further comprising
a third interlayer insulation film stacked on an upper side of the silicon compound film, wherein the third interlayer insulation film is embedded on an upper side of the recessed portion.

16 . The semiconductor device according to claim 15 , wherein
the first to third interlayer insulation films are flattened.

17 . The semiconductor device according to claim 11 , wherein
the film stack is a film in which an insulation film and a conductive film are alternately and repeatedly stacked.

18 . The semiconductor device according to claim 11 , wherein
the silicon compound film is a SiN film, a SiON film, a SiC film, or a SiBN film.

19 . The semiconductor device according to claim 15 , wherein
the third interlayer insulation film is a SiO film, a SiN film, a SiON film, a SiC film, or a SiBN film.

20 . The semiconductor device according to claim 11 , wherein
the recessed portion has a depth deeper than 300 nm.

Assignees

• Toshiba Kk

Inventors

• Tamura Shinpei

Classifications

• H01L27/1157

  Electricity · mapped topic

• H01L27/11575 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title