Double side via last method for double embedded patterned substrate

Patent metadata

Field	Value
Publication number	US-9659853-B2
Application number	US-201514696355-A
Country	US
Kind code	B2
Filing date	Apr 24, 2015
Priority date	Apr 24, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

First claim

What is claimed is:

1. An interposer substrate, comprising:
a dielectric layer with a first surface and a second surface opposite to the first surface, wherein the dielectric layer is formed of a same material throughout the dielectric layer;
a first circuit pattern embedded in the dielectric layer and disposed at the first surface of the dielectric layer;
a second circuit pattern embedded in the dielectric layer and disposed at the second surface of the dielectric layer;
a middle patterned conductive layer disposed within the dielectric layer and between the first circuit pattern and the second circuit pattern, wherein the middle patterned conductive layer is single layered;
at least one first conductive via connecting the first circuit pattern to the middle patterned conductive layer, each of the at least one first conductive via including a first end with a first width adjacent to the first circuit pattern and a second end with a second width adjacent to the middle patterned conductive layer, wherein the first width is greater than the second width; and
at least one second conductive via connecting the second circuit pattern to the middle patterned conductive layer, each of the at least one second conductive via including a third end with a third width adjacent to the second circuit pattern and a fourth end with a fourth width adjacent to the middle patterned conductive layer, wherein the third width is greater than the fourth width.

2. The interposer substrate according to claim 1 , wherein each of the at least one first conductive via decreases in size from the first width at the first end to the second width at the second end, and each of the at least one second conductive via decreases in size from the third width at the third end to the fourth width at the fourth end.

3. The interposer substrate according to claim 1 , wherein the dielectric layer comprises at least two dielectric sub-layers.

4. The interposer substrate according to claim 1 , wherein the middle patterned conductive layer comprises a middle circuit pattern.

5. The interposer substrate according to claim 1 , wherein the at least one first conductive via and the at least one second conductive via are substantially plane-symmetric with respect to a plane defined by the middle patterned conductive layer.

6. The interposer substrate according to claim 1 , the first circuit pattern comprising at least one first via pad, the second circuit pattern comprising at least one second via pad, and the middle patterned conductive layer comprising at least one middle via pad, wherein one of the at least one first conductive via is connected to the first circuit pattern at a respective first via pad and is connected to the middle patterned conductive layer at a respective middle via pad, and one of the at least one second conductive via is connected to the second circuit pattern at a respective second via pad and is connected to the middle patterned conductive layer at the respective middle via pad, and wherein a width of the respective middle via pad is less than or equal to a width of the respective first via pad or a width of the respective second via pad.

7. The interposer substrate according to claim 6 , wherein the respective middle via pad includes a top surface and a bottom surface, and both the top surface and the bottom surface of the respective middle via pad are substantially planar.

8. The interposer substrate according to claim 1 , the first circuit pattern comprising at least one first via pad, the second circuit pattern comprising at least one second via pad, and the middle patterned conductive layer comprising at least one middle via pad, wherein one of the at least one first conductive via is connected to the first circuit pattern at a respective first via pad having a fifth width and is connected to the middle patterned conductive layer at a respective middle via pad having a sixth width, and one of the at least one second conductive via is connected to the second circuit pattern at a respective second via pad having a seventh width and is connected to the middle patterned conductive layer at another respective middle via pad having an eighth width, and wherein the sixth width is less than or equal to the fifth width, and the eighth width is less than or equal to the seventh width.

9. The interposer substrate according to claim 8 , wherein each of the respective middle via pads has a substantially planar top surface and a substantially planar bottom surface.

10. A package structure, comprising:
a semiconductor device;
an interposer substrate, comprising:
a dielectric layer with a first surface and a second surface opposite to the first surface;
a first circuit pattern embedded in the dielectric layer and disposed at the first surface of the dielectric layer;
a second circuit pattern embedded in the dielectric layer and disposed at the second surface of the dielectric layer;

a middle patterned conductive layer disposed within the dielectric layer and between the first circuit pattern and the second circuit pattern, wherein the middle patterned conductive layer is single layered;
at least one first conductive via connecting the first circuit pattern to the middle patterned conductive layer, each of the at least one first conductive via including a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer; and
at least one second conductive via connecting the second circuit pattern to the middle patterned conductive layer, each of the at least one second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer;
wherein, for each of the at least one first conductive via, a width at the first end is greater than a width at the second end; and for each of the at least one second conductive via, a width at the third end is greater than a width at the fourth end;

a base substrate, wherein the interposer substrate is disposed between the semiconductor device and the base substrate and electrically connects the semiconductor device to the base substrate; and
an encapsulation layer over the base substrate, wherein the encapsulation layer encapsulates the semiconductor device and the interposer substrate.

11. The package structure according to claim 10 , wherein the first circuit pattern is electrically connected to the semiconductor device, and a line width of the first circuit pattern is in a range from 2 μm to 10 μm.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Lee Chih-Cheng
• Su Yuan-Chang

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W46/607

  Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title

• H10W46/301

  for alignment · CPC title

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title