Common contact leadframe for multiphase applications

Patent metadata

Field	Value
Publication number	US-10128173-B2
Application number	US-201615287368-A
Country	US
Kind code	B2
Filing date	Oct 6, 2016
Priority date	Oct 6, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

In some examples, a device includes an input leadframe segment and a reference leadframe segment that is electrically isolated from the input leadframe segment. The device further includes at least four transistors comprising at least two high-side transistors that are electrically connected to the input leadframe segment and at least two low-side transistors that are electrically connected to the reference leadframe segment. The device further includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors, each switching element of the at least two switching elements is electrically connected to a respective low-side transistor of the at least two low-side transistors, and the at least four transistors include at least one discrete transistor.

First claim

What is claimed is:

1. A device comprising:
an input leadframe segment;
a reference leadframe segment, wherein the reference leadframe segment is electrically isolated from the input leadframe segment;
at least four transistors comprising:
at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the input leadframe segment, and
at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference leadframe segment; and

at least two switching elements, wherein:
each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors,
each switching element of the at least two switching elements is electrically connected to a respective low-side transistor of the at least two low-side transistors, and
the at least four transistors include at least one discrete transistor, wherein the at least one discrete transistor is not integrated into a single semiconductor die with another transistor.

2. The device of claim 1 , wherein:
the at least two high-side transistors comprise at least two discrete transistors; and
the at least two low-side transistors comprise at least two discrete transistors.

3. The device of claim 1 , wherein each transistor of the at least four transistors comprises a discrete transistor.

4. The device of claim 1 , further comprising a molding compound, wherein:
the molding compound encapsulates the at least four transistors; and
the molding compound at least partially encapsulates the at least two switching elements.

5. The device of claim 1 , wherein each switching element of the at least two switching elements comprises an aluminum ribbon, a copper clip, or a wire bond.

6. The device of claim 1 , further comprising at least two switch leadframe segments, wherein each switching element of the at least two switching elements comprises:
a copper clip electrically connected to:
a respective high-side transistor of the at least two high-side transistors, and
a respective low-side transistor of the at least two low-side transistors; and

a foot portion electrically connected to a respective switch leadframe segment of the at least two switch leadframe segments.

7. The device of claim 1 , wherein:
a first foot portion of a first switching element of the at least two switching elements is adjacent to a respective high-side transistor of the at least two high-side transistors;
a second foot portion of a second switching element of the at least two switching elements is adjacent to a respective low-side transistor of the at least two low-side transistors; and
the first switching element is adjacent to the second switching element.

8. The device of claim 1 , wherein:
each high-side transistor of the at least two high-side transistors comprises a vertical high-side field-effect transistor (FET);
each low-side transistor of the at least two low-side transistors comprises a vertical low-side field-effect transistor (FET);
a drain terminal of each vertical high-side FET of the at least two high-side transistors is electrically connected to the input leadframe segment;
a source terminal of each vertical high-side FET of the at least two high-side transistors is electrically connected to a respective switching element of the at least two switching elements;
a drain terminal of each vertical low-side FET of the at least two low-side transistors is electrically connected to a respective switching element of the at least two switching elements; and
a source terminal of each vertical low-side FET of the at least two low-side transistors is electrically connected to the reference leadframe segment.

9. A method comprising:
electrically connecting at least two high-side transistors of at least four transistors to an input leadframe segment;
electrically connecting at least two low-side transistors of the at least four transistors to a reference leadframe segment, wherein the reference leadframe segment is electrically isolated from the input leadframe segment;
electrically connecting each respective switching element of at least two switching elements to a respective high-side transistor of the at least two high-side transistors; and
electrically connecting each respective switching element of at least two switching elements to a respective low-side transistor of the at least two low-side transistors, wherein the at least four transistors include at least one discrete transistor, wherein the at least one discrete transistor is not integrated into a single semiconductor die with another transistor.

10. The method of claim 9 , wherein each transistor of the at least four transistors comprises a discrete transistor.

11. The method of claim 9 , further comprising:
testing a performance of the at least one discrete transistor before electrically connecting the discrete transistor to the input leadframe segment or the reference leadframe segment; and
discarding the discrete transistor based on testing the performance of the discrete transistor.

12. The method of claim 9 , further comprising:
encapsulating the at least two high-side transistors and the at least two low-side transistors in a molding compound; and
at least partially encapsulating the at least two switching elements in the molding compound.

13. The method of claim 9 , wherein each switching element of the at least two switching elements comprises an aluminum ribbon, a copper clip, or a wire bond.

14. The method of claim 9 , further comprising electrically connecting a foot portion of each switching element of the at least two switching elements to a respective switch leadframe segment of at least two switch leadframe segments.

15. The method of claim 14 , wherein:
electrically connecting a first foot portion of a first switching element of the at least two switching elements to a first respective switch leadframe segment of the at least two switch leadframe segments; and
electrically connecting a second foot portion of a second switching element of the at least two switching elements to a second respective switch leadframe segment of the at least two switch leadframe segments, wherein:
the first switch leadframe segment is adjacent to a respective high-side transistor of the at least two high-side transistors,
the second switch leadframe segment is adjacent to a respective low-side transistor of the at least two low-side transistors, and
the first switching element is adjacent to the second switching element.

16. A multiphase power converter comprising:
an input leadframe segment;
a reference leadframe segment, wherein the reference leadframe segment is electrically isolated from the input leadframe segment;
at least four vertical transistors comprising:
at least two high-side vertical transistors, wherein each high-side vertical transistor of the at least two high-side vertical transistors is electrically connected to the input leadframe segment, and
at least two low-side vertical transistors, wherein each low-side vertical transistor of the at least two low-side transistors is electrically connected to the reference leadframe segment; and

at least two switching elements, wherein:
each switching element of the at least two switching elements is electrically connected to a respective high-side vertical transistor of the at least two high-side vertical transistors,
each switching element of the at least two switching e

Assignees

• Infineon Technologies Americas Corp

Inventors

• Cho Eung San

Classifications

• H10W72/07653

  changes in shapes · CPC title

• H10W72/534

  being rectangular · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title