Semiconductor integrated circuit and method for operating the same

Patent metadata

Field	Value
Publication number	US-9257907-B2
Application number	US-201314064522-A
Country	US
Kind code	B2
Filing date	Oct 28, 2013
Priority date	Dec 26, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A switching loss is reduced by reducing a deviation from the operational principle of zero-volt switching (ZVS). A semiconductor integrated circuit includes high-side switch elements Q 11 and Q 12 , a low-side switch element Q 2 , and a controller CNT. A decoupling capacitance Cin is coupled between one end of a high-side element and an earth potential, and the high-side element includes the first and second transistors Q 11 and Q 12 coupled in parallel. In changing the high-side elements from an on-state to an off-state, CNT controls Q 12 from an on-state to an off-state by delaying Q 12 relative to Q 11 . Q 11 and Q 12 are divided into a plurality of parts inside a semiconductor chip Chip 1 , a plurality of partial first transistors formed by dividing Q 11 and a plurality of partial second transistors formed by dividing Q 12 are alternately arranged in an arrangement direction of Q 11 and Q 12 , inside the semiconductor chip Chip 1.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising a high-side switch element, a low-side switch element, and a controller,
wherein an input voltage can be supplied to one end of the high-side switch element via a decoupling inductor, other end of the high-side switch element and one end of the low-side switch element are coupled to a switching node, and other end of the low-side switch element can be coupled to an earth potential,
wherein the controller can drive the high-side switch element in an on-state and an off-state,
wherein the switching node can be coupled to a low pass filter including a smoothing inductor and a smoothing capacitor,
wherein a decoupling capacitor can be coupled between the one end of the high-side switch element and the earth potential,
wherein the high-side switch element includes a first transistor and a second transistor whose current paths are coupled in parallel between the one end of the high-side switch element and the other end of the high-side switch element,
wherein in changing a state between the one end of the high-side switch element and the other end of the high-side switch element from an on-state to an off-state, the controller controls the second transistor from the on-state to the off-state by delaying the second transistor relative to the first transistor,
wherein each transistor of the first transistor and the second transistor is formed to be divided into a plurality of parts, inside a semiconductor chip, and
wherein a plurality of partial first transistors formed by dividing the first transistor and a plurality of partial second transistors formed by dividing the second transistor are alternately arranged in an arrangement direction of the first transistor and the second transistor, inside the semiconductor chip.

2. The semiconductor integrated circuit according to claim 1 ,
wherein the low-side switch element includes a third transistor whose current path is coupled between the switching node and the earth potential.

3. The semiconductor integrated circuit according to claim 2 ,
wherein the controller generates a first high-side driving signal for driving a control input terminal of the first transistor, a second high-side driving signal for driving a control input terminal of the second transistor, and a low-side driving signal for driving a control input terminal of the third transistor, and
wherein the first high-side driving signal and the second high-side driving signal are substantially in-phase, whereas the first high-side driving signal as well as the second high-side driving signal, and the low-side driving signal are substantially anti-phase.

4. The semiconductor integrated circuit according to claim 3 ,
wherein an output voltage of a DC-DC converter generated from the low pass filter is set by an on period during which the high-side switch element is in the on-state, an off period during which the high-side switch element is in the off-state, and the input voltage.

5. The semiconductor integrated circuit according to claim 4 ,
wherein the first transistor, the second transistor, and the third transistor are N-channel MOS transistors, respectively.

6. The semiconductor integrated circuit according to claim 5 ,
wherein the first transistor and the second transistor as the high-side switch elements are formed in a first semiconductor chip,
wherein the third transistor as the low-side switch element is formed in a second semiconductor chip,
wherein the controller is formed in a third semiconductor chip, and
wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are sealed into one package.

7. The semiconductor integrated circuit according to claim 6 ,
wherein the first transistor and the second transistor as the high-side switch elements are formed by a trench-gate-type N-channel vertical MOS transistor structure, and
wherein a plurality of trench gates of the first transistor and a plurality of trench gates of the second transistor are alternately arranged in the arrangement direction of the first transistor and the second transistor, inside the first semiconductor chip.

8. The semiconductor integrated circuit according to claim 7 ,
wherein the third transistor as the low-side switch element is formed by the trench-gate-type N-channel vertical MOS transistor structure.

9. The semiconductor integrated circuit according to claim 8 ,
wherein the one package, the decoupling inductor, the decoupling capacitor, the smoothing inductor, and the smoothing capacitor comprise a DC-DC converter of a switching regulator system.

10. The semiconductor integrated circuit according to claim 5 ,
wherein the first transistor and the second transistor as the high-side switch elements, the third transistor as the low-side switch element, and the controller are integrated and formed in a single semiconductor chip, and
wherein the single semiconductor chip is sealed into one package.

11. The semiconductor integrated circuit according to claim 10 ,
wherein the first transistor and the second transistor as the high-side switch elements are formed by a planer-type N-channel lateral MOS transistor structure, and
wherein a plurality of gates of the first transistor and a plurality of gates of the second transistor are alternately arranged in the arrangement direction of the first transistor and the second transistor, inside the single semiconductor chip.

12. The semiconductor integrated circuit according to claim 11 ,
wherein the third transistor as the low-side switch element is formed by the planer-type N-channel lateral MOS transistor structure inside the single semiconductor chip.

13. The semiconductor integrated circuit according to claim 12 ,
wherein the single semiconductor chip, the decoupling inductor, the decoupling capacitor, the smoothing inductor, and the smoothing capacitor comprise a DC-DC converter of a switching regulator system.

14. A method for operating a semiconductor integrated circuit comprising a high-side switch element, a low-side switch element, and a controller,
wherein an input voltage can be supplied to one end of the high-side switch element via a decoupling inductor, other end of the high-side switch element and one end of the low-side switch element are coupled to a switching node, and other end of the low-side switch element can be coupled to an earth potential,
wherein the controller can drive the high-side switch element in an on-state and an off-state,
wherein the switching node can be coupled to a low pass filter including a smoothing inductor and a smoothing capacitor,
wherein a decoupling capacitor can be coupled between the one end of the high-side switch element and the earth potential,
wherein the high-side switch element includes a first transistor and a second transistor whose current paths are coupled in parallel between the one end of the high-side switch element and the other end of the high-side switch element,
wherein in changing the state between the one end of the high-side switch element and the other end of the high-side switch element from an on-state to an off-state, the controller controls the second transistor from the on-state to the off-state by delaying the second transistor relative to the first transistor,
wherein each transistor of the first transistor and the second transistor is formed to be divided into a plurality of parts, inside a semiconductor chip, and
wherein a plurality of partial first transistors formed by dividing the first transistor and a plurality of partial second transistors formed by dividing the second transist

Assignees

• Renesas Electronics Corp

Inventors

• Nomiyama Takahiro
• Tateno Koji
• Kondo Daisuke

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H03K2217/0072

  Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load · CPC title