DC/DC converter circuit of semiconductor device having a first transistor of a normally-off type and a second transistor of a normally-on type

Patent metadata

Field	Value
Publication number	US-9324851-B2
Application number	US-201314060601-A
Country	US
Kind code	B2
Filing date	Oct 22, 2013
Priority date	Oct 23, 2012
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A semiconductor device including a DC/DC converter circuit, in which the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected to an input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a DC/DC converter circuit,
wherein the DC/DC converter circuit includes
a first transistor of a normally-off type, having a first drain electrode connected to an input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer;
a second transistor of a normally-on type, having a second drain electrode connected to the first source electrode and a grounded second source electrode, which is formed in the first compound semiconductor substrate;
a drain pad disposed opposite to the second transistor across the first transistor, the first drain electrode of the first transistor being connected to the drain pad;
a source pad disposed opposite to the first transistor across the second transistor, the grounded second source electrode of the second transistor being connected to the source pad; and
a first pad disposed between the first transistor and the second transistor, the first source electrode of the first transistor and the second drain electrode of the second transistor being connected to the first pad,
wherein a recess is formed in a surface of the first compound semiconductor substrate,
wherein the first transistor has a first gate electrode of which at least a portion is located within the recess, and
wherein the second transistor has a second gate electrode of which a lower end is located above a surface of the first compound semiconductor substrate.

2. The semiconductor device according to claim 1 , wherein a protection circuit is not provided between the first transistor and the input terminal.

3. The semiconductor device according to claim 1 , wherein the first compound semiconductor substrate has a GaN layer and an AlGaN layer provided over the GaN layer.

4. The semiconductor device according to claim 1 , wherein the DC/DC converter circuit has a control circuit which is connected to a first gate electrode constituting the first transistor and a second gate electrode constituting the second transistor, and is constituted by a silicon transistor.

5. The semiconductor device according to claim 4 , wherein a first semiconductor chip including the first transistor and the second transistor and a second semiconductor chip including the control circuit are mounted over the same first compound semiconductor substrate.

Assignees

• Renesas Electronics Corp

Inventors

• Nega Ryohei
• Miura Yoshinao

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title