Shift register, gate driving circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-9824659-B2
Application number	US-201615327852-A
Country	US
Kind code	B2
Filing date	Mar 24, 2016
Priority date	Sep 1, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A shift register, a gate driving circuit and a display apparatus are provided. The shift register comprises a pull-up node control unit, a pull-down node control unit, a pull-up output unit, a noise reduction unit, and a touch scanning control unit. Herein, the pull-up node control unit is connected to a first input terminal, a second input terminal, a first power supply terminal, a second power supply terminal, and a pull-up node (PU); the pull-down node control unit is connected to a high level terminal (VGH), a low level terminal (VGL) and the pull-up node (PU) and a pull-down node (PD); the pull-up output unit is connected to a clock signal input terminal (CLK), the pull-up node (PU), a signal output terminal (Output); the noise reduction unit is connected to the pull-up node (PD) and the low level terminal (VGL); the touch scanning control unit is connected to a control signal input terminal (SW), the pull-up node (PU), the signal output terminal (Output), and the low level terminal (VGL).

First claim

What is claimed is:

1. A shift register, comprising:
a pull-up node control unit, connected to a first input terminal, a second input terminal, a first power supply terminal, a second power supply terminal, and a pull-up node, and configured to control a potential of the pull-up node according to a control signal input by the first input terminal and the second input terminal, the pull-up node being a connection node between the pull-up node control unit and the pull-up output unit;
a pull-down node control unit, connected to a high level terminal, a low level terminal and the pull-up node and a pull-down node, and configured to control a potential of the pull-down node according to the potential of the pull-up node, the pull-down node being a connection node between the pull-down node control unit and the noise reduction unit;
a pull-up output unit, connected to a clock signal input terminal, the pull-up node, a signal output terminal, and configured to control a potential of the signal output terminal according to the potential of the pull-up node and a clock signal input by the clock signal input terminal;
a noise reduction unit, connected to the pull-up node, the pull-down node, the low level terminal and the signal output terminal, and configured to reduce noise for the pull-up node and the signal output terminal through a signal input by the low level terminal under the control of the pull-down node;
a touch scanning control unit, connected to a control signal input terminal, the pull-up node, the signal output terminal, and the low level terminal, and configured to control an operation time in a touch scanning phase and potentials of the pull-up node and the signal output terminal according to the signal input by the control signal input terminal.

2. The shift register according to claim 1 , wherein the touch scanning control unit makes the touch scanning phase occur between display phases of two adjacent frame pictures under the control of a signal input by the control signal input terminal.

3. The shift register according to claim 1 , wherein the touch scanning control unit makes the touch scanning phase occur in a display phase of each frame picture under the control of the signal input by the control signal input terminal.

4. The shift register according to claim 1 , wherein the pull-up node control unit comprises: a first transistor and a second transistor;
a first electrode of the first transistor is connected to a first power supply terminal, a second electrode thereof is connected to the pull-up node, and a control electrode thereof is connected to the first input terminal; and
a first electrode of the second transistor is connected to the pull-up node, a second electrode thereof is connected to the second power supply terminal, and a control electrode thereof is connected to the second input terminal.

5. The shift register according to claim 1 , wherein the first power supply terminal is a high voltage power supply terminal, and the second power supply terminal is a low voltage power supply terminal; the signal input by the first input terminal is a signal output by a signal output terminal of a previous stage of shift register of the shift register, and the signal input by the second input terminal is a signal output by a signal output terminal of a next stage of shift register of the shift register, such that the shift register realizes displaying and scanning forwards.

6. The shift register according to claim 1 , wherein the first power supply terminal is a high voltage power supply terminal, and the second power supply terminal is a low voltage power supply terminal; the signal input by the first input terminal is a signal output by a signal output terminal of the next stage of shift register of the shift register, and the signal input by the second input terminal is a signal output by a signal output terminal of the previous stage of shift register of the shift register; or, the first power supply terminal is a low voltage power supply terminal, and the second power supply terminal is a high voltage power supply terminal; the signal input by the first input terminal is a signal output by a signal output terminal of the previous stage of shift register of the shift register, and the signal input by the second input terminal is a signal output by a signal output terminal of the next stage of shift register of the shift register, such that the shift register realizes displaying and scanning forwards.

7. The shift register according to claim 1 , wherein the pull-up output unit comprises: a third transistor and a storage capacitor;
a first electrode of the third transistor is connected to the clock signal input terminal, a second electrode thereof is connected to a signal output terminal, and a control electrode thereof is connected to the pull-up node; and
a first terminal of the storage capacitor is connected to the pull-up node, and a second terminal thereof is connected to the signal output terminal.

8. The shift register according to claim 1 , wherein the pull-down node control unit comprises: a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor;
a first electrode of the sixth transistor is connected to the pull-down node, a second electrode thereof is connected to the low level terminal, and a control electrode thereof is connected to the pull-up node;
a first electrode of the seventh transistor is connected to a control electrode of the eighth transistor and a second electrode of the ninth transistor, a second electrode thereof is connected to the low level terminal, and a control electrode thereof is connected to the pull-up node;
a first electrode of the eighth transistor is connected to the high level terminal, a second electrode thereof is connected to the pull-down node, and the control electrode thereof is connected to the second electrode of the ninth transistor;
a first electrode and a control electrode of the ninth transistor are both connected to the high level terminal, and the second electrode thereof is connected to the control electrode of the eighth transistor.

9. The shift register according to claim 1 , wherein the noise reduction unit comprises: a fourth transistor and a tenth transistor; wherein
a first electrode of the fourth transistor is connected to the signal output terminal, a second electrode thereof is connected to the low level terminal, and a control electrode thereof is connected to the pull-down node; and
a first electrode of the tenth transistor is connected to the pull-up node, a second electrode thereof is connected to the low level terminal, and a control electrode thereof is connected to the pull-down node.

10. The shift register according to claim 1 , wherein the touch scanning control unit comprises: a fifth transistor, an eleventh transistor, and a twelfth transistor; wherein
a first electrode of the fifth transistor is connected to the signal output terminal, a second electrode thereof is connected to the low level terminal, and a control electrode thereof is connected to the control signal input terminal;
a first electrode of the eleventh transistor is connected to a second electrode of the twelfth transistor, and a second electrode and a control electrode are both connected to the pull-up node; and
a first electrode and a control electrode of the twelfth transistor are both connected to the control signal input terminal, and the second electrode thereof is connected to the first electrode of the eleventh transistor.

11. A gate driving circuit, comprising a plurality of shift registers connected in cascades according to claim 1 .

12. A display apparatus, comprising the ga

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Gu Honggang
• Che Chuncheng
• Li Xiaohe
• Shao Xianjie
• Song Jie

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G06F3/041

  Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title