P-N bimodal transistors

Patent metadata

Field	Value
Publication number	US-10121891-B2
Application number	US-201615364971-A
Country	US
Kind code	B2
Filing date	Nov 30, 2016
Priority date	Sep 22, 2015
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

First claim

What is claimed is:

1. A transistor, comprising:
a doped layer having a first conductivity type;
a buried layer in the doped layer, the buried layer having a second conductivity type opposite the first conductivity type;
a first terminal region having a first n-doped region and a first p-doped region adjacent to the first n-doped region;
a second terminal region having a second n-doped region and a second p-doped region adjacent to the second n-doped region;
a surface doped region having the second conductivity type and positioned between the first and second terminal regions;
a first gate positioned above and between the first p-doped region and the surface doped region; and
a second gate positioned above and between the surface doped region and the second n-doped region.

2. The transistor of claim 1 , wherein:
the first p-doped region positioned laterally between the first n-doped region and the surface doped region; and
the second n-doped region positioned laterally between the surface doped region and the second p-doped region.

3. The transistor of claim 1 , wherein the first gate is associated with a p-channel between the first p-doped region and the second p-doped region.

4. The transistor of claim 1 , wherein the second gate is associated with an n-channel between the first n-doped region and the second n-doped region.

5. The transistor of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

6. The transistor of claim 5 , further comprising:
a third p-doped region inside the surface doped region and having a higher doping concentration than the surface doped region, the third p-doped region coupled to the second p-doped region,
wherein the second gate is positioned above and between the third p-doped region and the second n-doped region.

7. The transistor of claim 5 , further comprising:
a p-doped well region surrounding the second terminal region.

8. The transistor of claim 5 , further comprising:
n-doped well region surrounding the first terminal region.

9. The transistor of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

10. The transistor of claim 9 , further comprising:
a third n-doped region inside the surface doped region and having a higher doping concentration than the surface doped region, the third n-doped region coupled to the first n-doped region,
wherein the first gate is positioned above and between the first p-doped region and the third n-doped region.

11. The transistor of claim 1 , wherein the first n-doped region abuts the first p-doped region.

12. The transistor of claim 1 , wherein the second n-doped region abuts the second p-doped region.

13. The transistor of claim 1 , wherein the first n-doped region abuts the first p-doped region and the second n-doped region abuts the second p-doped region.

14. A transistor, comprising:
n-doped layer;
a p-doped buried layer in the n-doped layer;
a first terminal region having a first n-doped region and a first p-doped region adjacent to the first n-doped region;
a second terminal region having a second n-doped region and a second p-doped region adjacent to the second n-doped region;
a p-doped surface region positioned between the first and second terminal regions;
a first gate positioned above and between the first p-doped region and the p-doped surface region; and
a second gate positioned above and between the p-doped surface region and the second n-doped region.

15. The transistor of claim 14 , wherein:
the first p-doped region positioned laterally between the first n-doped region and the p-doped surface region; and
the second n-doped region positioned laterally between the p-doped surface region and the second p-doped region.

16. The transistor of claim 14 , wherein:
the first gate is associated with a p-channel between the first p-doped region and the second p-doped region; and
the second gate is associated with an n-channel between the first n-doped region and the second n-doped region.

17. The transistor of claim 14 , further comprising:
a third p-doped region inside the p-doped surface region and having a higher doping concentration than the p-doped surface region, the third p-doped region coupled to the second p-doped region,
wherein the second gate is positioned above and between the third p-doped region and the second n-doped region.

18. The transistor of claim 14 , further comprising:
a p-doped well region surrounding the second terminal region,
wherein the p-doped buried layer is connected to the p-doped surface region and the p-doped well region.

19. The transistor of claim 14 , further comprising:
an n-doped well region surrounding the first terminal region.

20. The transistor of claim 14 , wherein the first n-doped region abuts the first p-doped region.

21. The transistor of claim 14 , wherein the second n-doped region abuts the second p-doped region.

22. The transistor of claim 14 , wherein the first n-doped region abuts the first p-doped region and the second n-doped region abuts the second p-doped region.

23. A transistor, comprising:
a p-doped layer;
n-doped buried layer in the p-doped layer;
a first terminal region having a first n-doped region and a first p-doped region adjacent to the first n-doped region;
a second terminal region having a second n-doped region and a second p-doped region adjacent to the second n-doped region;
an n-doped surface region positioned between the first and second terminal regions;
a first gate positioned above and between the first p-doped region and the n-doped surface region; and
a second gate positioned above and between the n-doped surface region and the second n-doped region.

24. The transistor of claim 23 , wherein:
the first p-doped region positioned laterally between the first n-doped region and the n-doped surface region; and
the second n-doped region positioned laterally between the n-doped surface region and the second p-doped region.

25. The transistor of claim 24 , wherein the first n-doped region abuts the first p-doped region.

26. The transistor of claim 24 , wherein the second n-doped region abuts the second p-doped region.

27. The transistor of claim 24 , wherein the first n-doped region abuts the first p-doped region and the second n-doped region abuts the second p-doped region.

28. The transistor of claim 23 , wherein:
the first gate is associated with a p-channel between the first p-doped region and the second p-doped region; and
the second gate is associated with an n-channel between the first n-doped region and the second n-doped region.

29. The transistor of claim 23 , further comprising:
a third n-doped region inside the n-doped surface region and having a higher doping concentration than the n-doped surface region, the third n-doped region coupled to the first n-doped region,
wherein the first gate is positioned above and between the first p-doped region and the third n-doped region.

30. A method of making a transistor, comprising:
providing a doped layer having a first conductivity type;
providing a buried layer in the doped layer, the buried layer having a second conductivity type opposite the first conductivity type;
providing a first terminal region having a first n-doped region and a first p

Assignees

• Texas Instruments Inc

Inventors

• Zhang Yongxi
• Pendharkar Sameer P
• Edwards Henry Litzmann

Classifications

• H01L29/063

  Electricity · mapped topic

• H01L29/7835

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/66681

  Electricity · mapped topic

• H01L29/7824

  Electricity · mapped topic