High voltage multiple channel LDMOS

Patent metadata

Field	Value
Publication number	US-9245998-B2
Application number	US-201414578710-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Dec 29, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

First claim

What is claimed is:

1. A process of forming an integrated circuit containing an LDNMOS transistor with multiple vertical current channels and a horizontal current channel, comprising the steps:
forming a buried n-type buried diffusion on a p-type substrate;
forming a p-type buried diffusion contained in the n-type buried diffusion;
forming a plurality of vertical n-type extended drain diffusions over the p-type buried diffusion and between a LDNMOS transistor gate and the LDNMOS drain;
implanting pwell dopant to form the body of the LDNMOS and to form a plurality of vertical pwell finger diffusions between the vertical n-type extended drain diffusions;
implanting p-type dopant at low energy into the channel of an NMOS transistor to set a turn on voltage of the NMOS transistor and into a channel of the LDNMOS transistor to set a turn on voltage; forming an NMOS transistor gate, a PMOS transistor gate, and the LDNMOS transistor gate;
forming dielectric sidewalls on the NMOS transistor gate, the PMOS transistor gate, and the LDNMOS transistor gate;
forming source and drain diffusions of the NMOS transistor self-aligned to the dielectric sidewalls on the NMOS transistor gate; and
forming an LDNMOS source self-aligned to the dielectric sidewalls on the LDNMOS transistor gate and forming an LDNMOS drain wherein the plurality of vertical n-type extended drain diffusions form a plurality of vertical LDNMOS channels between the source and the drain and wherein a horizontal LDMOS channel is formed between the LDNMOS source and LDNMOS drain in the buried n-type diffusion which lies under the buried p-type diffusion and over the p-type substrate.

2. The process of claim 1 further comprising:
during the step of forming the buried p-type diffusion forming a plurality of buried p-type diffusions wherein plurality of buried p-type diffusions underlie the plurality of vertical pwell finger diffusions.

3. The process of claim 1 , wherein
the buried n-type dopant is phosphorus with a concentration in the range of about 3E12/cm 2 to 8E12/cm 2 that is implanted with energy in the range of about 500 KeV to 3000 KeV;
the buried p-type dopant is boron with a concentration in the range of about 4E12/cm 2 to 1E13/cm 2 that is implanted with an energy in the range of about 50 KeV to 300 KeV;
the n-type vertical extended drain dopant is phosphorus with a concentration in the range of about 2E12/cm 2 to 8E12/cm 2 that is implanted with energy in the range of about 200 KeV to 600 KeV; and
the pwell dopant is boron with a concentration in the range of about 1E13/cm 2 to 2E14/cm 2 that is implanted with an energy in the range of about 50 KeV to 200 KeV.

4. A process of forming an integrated circuit containing an LDNMOS transistor with multiple vertical current channels and a horizontal current channel, comprising the steps:
forming a buried n-type buried diffusion on a p-type substrate;
forming a p-type buried diffusion contained in the n-type buried diffusion;
forming a plurality of vertical n-type extended drain diffusions over the p-type buried diffusion and between a LDNMOS transistor gate and the LDNMOS drain;
implanting pwell dopant to form the body of the LDNMOS and to form a plurality of vertical pwell finger diffusions between the vertical n-type extended drain diffusions;
implanting p-type dopant at low energy into the channel of an NMOS transistor to set a turn on voltage of the NMOS transistor and into a channel of the LDNMOS transistor to set a turn on voltage;
forming an NMOS transistor gate, a PMOS transistor gate, and a first LDNMOS transistor gate and a second LDNMOS transistor gate;
forming dielectric sidewalls on the NMOS transistor gate, the PMOS transistor gate, and the first LDNMOS transistor gate and the second LDNMOS transistor gate;
forming source and drain diffusions of the NMOS transistor self-aligned to the dielectric sidewalls on the NMOS transistor gate; and
forming an LDNMOS source self-aligned to the dielectric sidewalls on the first LDNMOS transistor gate and the second LDNMOS transistor gate wherein the LDNMOS source lies between the first and second LDNMOS transistor gates and forming an LDNMOS drain wherein the LDNMOS drain is shared by the first and second LDNMOS transistor gates wherein the plurality of vertical n-type extended drain diffusions form a plurality of vertical LDNMOS channels between the source and the drain of the first LDNMOS transistor and wherein a first horizontal LDNMOS channel is formed between the source and drain of the first LDNMOS transistor in the buried n-type diffusion which lies under the buried p-type diffusion and over the p-type substrate and wherein a second horizontal channel is formed between the source and drain of the second LDNMOS transistor in the buried n-type diffusion.

5. The process of claim 4 further comprising:
during the step of forming the buried p-type diffusion forming a plurality of buried p-type diffusions wherein plurality of buried p-type diffusions underlie the plurality of vertical pwell finger diffusions.

6. The process of claim 4 , wherein
the buried n-type dopant is phosphorus with a concentration in the range of about 3E12/cm 2 to 8E12/cm 2 that is implanted with energy in the range of about 500 KeV to 3000 KeV;
the buried p-type dopant is boron with a concentration in the range of about 4E12/cm 2 to 1E13/cm 2 that is implanted with an energy in the range of about 50 KeV to 300 KeV;
the n-type vertical extended drain dopant is phosphorus with a concentration in the range of about 2E12/cm 2 to 8E12/cm 2 that is implanted with energy in the range of about 200 KeV to 600 KeV; and
the pwell dopant is boron with a concentration in the range of about 1E13/cm 2 to 2E14/cm 2 that is implanted with an energy in the range of about 50 KeV to 200 KeV.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Yongxi
• Pendharkar Sameer P

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/22

  using masks · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title