Byte level granularity buffer overflow detection for memory corruption detection architectures

Patent metadata

Field	Value
Publication number	US-10095573-B2
Application number	US-201715708079-A
Country	US
Kind code	B2
Filing date	Sep 18, 2017
Priority date	Mar 2, 2015
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

Memory corruption detection technologies are described. A processor can include a memory to store a memory corruption detection (MCD) table. A processor core of the processor can receive, from an application, an allocation request for an allocation of a memory object within a contiguous memory block in the memory. The processor core can allocate the contiguous memory block in view of a size of the memory object requested and write MCD meta-data into the MCD table, including a MCD identifier (ID) associated with the contiguous memory block and a MCD border value indicating a size of a memory region of the contiguous memory block.

First claim

What is claimed is:

1. A processor comprising:
a memory to store a memory corruption detection (MCD) table; and
a processor core coupled to the memory, wherein the processing core is to:
receive, from an application, an allocation request for an allocation of a memory object within a contiguous memory block in the memory;
allocate the contiguous memory block in view of a size of the memory object requested; and
write a MCD meta-data into the MCD table, wherein the MCD meta-data comprises:
a MCD identifier (ID) associated with the contiguous memory block; and
a MCD border value indicating how many bytes of the contiguous memory block are unusable.

2. The processor of claim 1 , wherein the MCD ID is one byte and the MCD border value is one byte, and wherein the MCD meta-data is a word.

3. The processor of claim 1 , wherein:
the contiguous memory block comprises a usable memory region and an unusable memory region, wherein the unusable memory region corresponds to a number of bytes from an end of the contiguous memory block that is unusable as indicated by the MCD border value.

4. The processor of claim 3 , wherein the processing core is further to:
receive, from the application, a memory access request comprising a pointer indicating a location in the memory and a second MCD ID;
compare the MCD ID to the second MCD ID to determine when the data is from the memory object indicated by the pointer; and
retrieve data stored at the location based on the pointer in the memory access request.

5. The processor claim 4 , wherein the processing core is further to determine when the data is from the usable memory region based on the MCD border value.

6. The processor of claim 4 , wherein the processor core is further to send, to the application, a fault message when a fault event when at least one the MCD ID does not match the second MCD ID or the memory access is within the unusable memory region.

7. The processor of claim 3 , wherein the processing core is further to determine the usable memory region by:
subtracting the MCD border value from a size value of the contiguous memory block to obtain a border location value; and
identifying a MCD border location in the contiguous memory block based on border location value, wherein the MCD border location indicates a boundary between the usable memory region and the unusable memory region.

8. The processor of claim 7 , wherein the size of the contiguous memory block is 64 bytes.

9. The processor of claim 3 , wherein the entire contiguous memory block is the usable memory region when the MCD border value is zero.

10. A processor comprising:
a memory; and
a processor core coupled to the memory, wherein the processing core is to:
receive, from an application an allocation request for a memory object to be stored within one or more contiguous memory blocks in the memory, wherein the allocation request specifies a size of the memory object;
allocate the one or more contiguous memory blocks for the memory object in view of the size of the memory object; and
write allocation data into the memory, the allocation data comprising for each one of the one or more contiguous memory blocks a unique identifier associated with the memory object and a border value indicating how many bytes of the respective one of the one or more contiguous memory blocks are unusable.

11. The processor of claim 10 , wherein a first contiguous memory block of the one or more contiguous memory blocks comprises a first memory region and a second memory region, wherein the first memory region is a used portion of the one or more contiguous memory blocks, and wherein the first memory region corresponds to a number of bytes from an end of the first contiguous memory block that is unusable as indicated by the border value.

12. The processor of claim 10 , wherein a first contiguous memory block of the one or more contiguous memory blocks comprises a first memory region and a second memory region, wherein the first memory region is an unused portion of one or more contiguous memory blocks, and wherein the second memory region corresponds to a number of bytes from an end of the first contiguous memory block that is unusable as indicated by the border value.

13. The processor of claim 10 , wherein the processor core is further to:
create a pointer with a memory address of the memory object and the unique identifier associated with the memory object; and
send, to the application, the pointer.

14. The processor of claim 10 , wherein the entire contiguous memory block is a usable memory region when the border value is zero.

15. A processor comprising:
a memory; and
a processor core coupled to the memory, wherein the processing core is to:
receive, from an application an allocation request for a memory object to be stored within one or more contiguous memory blocks in the memory, wherein the allocation request specifies a size of the memory object;
allocate the one or more contiguous memory blocks for the memory object in view of the size of the memory object, wherein a contiguous memory block of the one or more contiguous memory blocks comprise a first memory region and a second memory region; and
write allocation data into the memory, the allocation data comprising a unique identifier associated with the memory object and a border value indicating a size of the first memory region, wherein the allocation data comprises a first byte for the unique identifier and a second byte for the border value.

16. The processor of claim 15 , wherein at least one of the one or more contiguous memory blocks is a fixed size.

17. A system comprising:
a memory device to store data according to a fixed-size memory blocks; and
a processor coupled to the memory device, wherein the processor is to:
receive, from an application, an allocation request for an allocation of a memory object within a contiguous memory block in the memory, wherein the allocation request specifies a size of the memory object;
allocate the contiguous memory block in view of the size of the memory object; and
write meta-data into at a table accessible by the processor, the meta-data comprising:
an identifier (ID) associated with the contiguous memory block; and
a border value indicating how many bytes of the contiguous memory block are unusable.

18. The system of claim 17 , wherein the processor is further to:
receive, from the application, a memory access request to access data of the memory object, wherein the memory access request comprises:
a pointer indicating a location in the memory of the memory object; and
a current identifier;
determine whether the current identifier matches the identifier stored in the table;
send, to the application, a fault message when the current identifier does not match the identifier stored in the table; and
retrieve and send, to the application, data stored at the location when the current identifier matches the identifier stored in the table.

19. The system of claim 17 , wherein the identifier is one byte and the border value is one byte.

20. The system of claim 17 , wherein the processor is further to determine an usable memory region of the contiguous memory block by:
subtracting the border value from a size value of the contiguous memory block to obtain a border location value; and
identifying a border location in the contiguous memory block based on border location value, wherein the border location indicates a boundary between a usable memory region and an unusable memory re

Assignees

• Intel Corp

Inventors

• Stark Tomer
• Tal Ady
• Gabor Ron
• Nuzman Joseph

Classifications

• G06F11/1064

  in cache or content addressable memories · CPC title

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/079 Primary

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title