FinFETs and methods of forming FinFETs

Patent metadata

Field	Value
Publication number	US-9953874-B2
Application number	US-201615286280-A
Country	US
Kind code	B2
Filing date	Oct 5, 2016
Priority date	Apr 28, 2016
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

An embodiment is a method including forming a multi-layer stack over a substrate, the multi-layer stack including alternating first layers and second layers, patterning the multi-layer stack to form a fin, forming an isolation region surrounding the fin, an upper portion of the fin extending above a top surface of the isolation region, forming a gate stack on sidewalls and a top surface of the upper portion of the fin, the gate stack defining a channel region of the fin, and removing the first layers from the fin outside of the gate stack, where after the removing the first layers, the channel region of the fin includes both the first layers and the second layers.

First claim

What is claimed is:

1. A method comprising:
forming a multi-layer stack over a substrate, the multi-layer stack comprising alternating first layers and second layers;
patterning the multi-layer stack to form a plurality of fins; and
performing a fin cut process to remove some of the plurality of fins, wherein after the fin cut process, a first fin remains;
forming an isolation region surrounding the first fin, an upper portion of the first fin extending above a top surface of the isolation region;
forming a gate stack on sidewalls and a top surface of the upper portion of the first fin, the gate stack defining a channel region of the first fin; and
removing the first layers from the first fin outside of the gate stack, wherein after the removing the first layers, the channel region of the first fin includes both the first layers and the second layers.

2. The method of claim 1 further comprising:
removing the second layers from the first fin outside of the gate stack, the removing the second layers forming recesses in the first fin, wherein after the removing the second layers, the channel region of the first fin includes both the first layers and the second layers.

3. The method of claim 2 further comprising:
epitaxially growing source/drain regions in the recesses of the first fin.

4. The method of claim 1 , wherein each of the first layers is compressively strained, and each of the second layers is tensilely strained.

5. The method of claim 1 , wherein each of the first layers is tensilely strained, and each of the second layers is compressively strained.

6. The method of claim 1 , wherein the multi-layer stack comprises strained layers.

7. The method of claim 1 , wherein removing the first layers from the first fin outside of the gate stack comprises selectively etching the first layers outside of the gate stack.

8. A method comprising:
forming a fin over a substrate, the fin comprising alternating first layers and second layers;
forming an isolation region surrounding the fin, an upper portion of the fin extending above a top surface of the isolation region;
forming a first gate stack on sidewalls and a top surface of the upper portion of the fin, the first gate stack defining a channel region of the fin;
removing the first layers from the fin outside of the first gate stack in a first removal process, wherein after the first removal process, the second layers remain outside the first gate stack; and
after the first removal process, removing the second layers from the fin outside of the first gate stack in a second removal process, the second removal process forming recesses in the fin outside of the first gate stack, wherein after the removing the second layers, the channel region of the fin includes both the first layers and the second layers.

9. The method of claim 8 further comprising:
epitaxially growing source/drain regions in the recesses of the fin.

10. The method of claim 8 further comprising:
forming a plurality of fins over the substrate; and
performing a fin cut process to remove some of the plurality of fins, wherein after the fin cut process, at least one fin remains.

11. The method of claim 8 further comprising:
replacing the first gate stack with a second gate stack.

12. The method of claim 8 , wherein each of the first layers is compressively strained, and each of the second layers is tensilely strained.

13. The method of claim 8 , wherein after the first removal process and before the second removal process, there are voids between adjacent second layers in the fin.

14. A method comprising:
forming plurality of fins comprising a multi-layer stack, the multi-layer stack comprising alternating first layers and second layers;
performing a fin cut process to remove some of the plurality of fins, wherein after the fin cut process, at least two fins remain;
forming a first gate dielectric and a first gate electrode on sidewalls and a top surface of the at least two fins, the first gate dielectric and first gate electrode defining channel regions of the at least two fins;
selectively etching the first layers of the multi-layer stack using the first gate dielectric and the first gate electrode as a mask;
after selectively etching the first layers, etching the second layers using the first gate dielectric and the first gate electrode as a mask to form recesses in the at least two fins;
after etching the second layers, epitaxially growing source/drain regions in the recesses of the at least two fins; and
replacing the first gate dielectric and the first gate electrode with a second gate dielectric and a second gate electrode.

15. The method of claim 14 , wherein the selectively etching the first layers fully removes the first layers.

16. The method of claim 14 , wherein the etching the second layers is an anisotropic etch.

17. The method of claim 14 , wherein the etching the second layers is an isotropic etch.

18. The method of claim 14 , wherein the multi-layer stack comprises strained layers.

19. The method of claim 14 , wherein after selectively etching the first layers and before etching the second layers, there are voids between adjacent second layers in the at least two fins.

20. The method of claim 14 , wherein after performing the fin cut process, at least one of the first layers or second layers remains on the removed fins.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Cheng
• Lin Chih-Han
• Tseng Horng-Huei

Classifications

• H01L29/66545

  Electricity · mapped topic

• H01L21/823431 Primary

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title