Three-dimensional memory device with enhanced mechanical stability semiconductor pedestal and method of making thereof

Patent metadata

Field	Value
Publication number	US-10074666-B2
Application number	US-201715401426-A
Country	US
Kind code	B2
Filing date	Jan 9, 2017
Priority date	Jan 9, 2017
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses. At least an outer portion of the laterally protruding semiconductor portion can be oxidized to form a tubular semiconductor oxide spacer. Electrically conductive layers can be formed in the backside recesses to provide word lines for a three-dimensional memory device.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
a memory opening extending through the alternating stack, wherein sidewalls of the memory opening comprise sidewalls of the insulating layers;
a memory stack structure located inside the memory opening and comprising a memory film that contacts the sidewalls of the memory opening, and a vertical semiconductor channel contacting an inner sidewall of the memory film; and
a semiconductor pedestal underlying the memory stack structure and located at a lowest level among the electrically conductive layers, wherein the semiconductor pedestal includes a laterally protruding semiconductor portion having an outer sidewall that is located farther outward from a vertical axis extending through a geometrical center of the memory stack structure than an outermost sidewall of the memory stack structure is from the vertical axis,
wherein:
the semiconductor pedestal comprises a columnar semiconductor pedestal portion vertically extending through an entire thickness of the lowest level among the electrically conductive layers and contacting the memory stack structure;
the laterally protruding semiconductor portion surrounds the columnar semiconductor pedestal portion and has an annular shape;
a vertical interface between the laterally protruding semiconductor portion and the columnar semiconductor pedestal portion is vertically coincident with the outermost sidewall of the memory stack structure; and
the three-dimensional memory device comprises at least one feature selected from:
(a) a first feature that the laterally protruding semiconductor portion has a uniform lateral thickness throughout or curved outer sidewalls: or
(b) a second feature that the laterally protruding semiconductor portion has a different material composition than the columnar semiconductor pedestal portion.

2. The three-dimensional memory device of claim 1 , wherein:
the substrate comprises a single crystalline semiconductor material layer; and
the semiconductor pedestal comprises an epitaxial semiconductor material portion in epitaxial alignment with the single crystalline semiconductor material layer.

3. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the first feature.

4. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the second feature.

5. The three-dimensional memory device of claim 1 , wherein an entirety of the vertical interface between the laterally protruding semiconductor portion and the columnar semiconductor pedestal is vertically coincident with the sidewalls of the memory opening.

6. The three-dimensional memory device of claim 1 , further comprising a tubular semiconductor oxide spacer that laterally surrounds the semiconductor pedestal, wherein one of the electrically conductive layers located at the lowest level among the electrically conductive layers laterally surrounds the tubular semiconductor oxide spacer.

7. The three-dimensional memory device of claim 6 , wherein the tubular semiconductor oxide spacer comprises an oxide of a semiconductor material within a portion of the semiconductor pedestal that contacts the tubular semiconductor oxide spacer.

8. The three-dimensional memory device of claim 1 , wherein a bottom portion of the vertical semiconductor channel protrudes into an upper center portion of the semiconductor pedestal.

9. The three-dimensional memory device of claim 1 , wherein:
a first annular horizontal surface of the semiconductor pedestal that is adjoined to the outer sidewall of the laterally protruding semiconductor portion is in physical contact with a horizontal bottom surface of one of the insulating layers; and
a second annular horizontal surface of the semiconductor pedestal that is adjoined to the outer sidewall of the laterally protruding semiconductor portion is in physical contact with a horizontal top surface of a dielectric material layer underlying a bottommost layer among the electrically conductive layers.

10. The three-dimensional memory device of claim 9 , wherein:
a topmost surface of the semiconductor pedestal is located above a horizontal plane including the first annular horizontal surface of the semiconductor pedestal and within an area defined by a periphery of the sidewalls of the memory opening; and
a bottommost surface of the semiconductor pedestal is located below a horizontal plane including the second annular horizontal surface of the semiconductor pedestal and within the area defined by the periphery of the sidewalls of the memory opening.

11. The three-dimensional memory device of claim 1 , wherein:
the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack;
the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and
support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces.

12. The three-dimensional memory device of claim 1 , further comprising a backside blocking dielectric layer disposed between each neighboring pair of an electrically conductive layer and an insulating layer and extending from a bottommost layer within the alternating stack to a topmost layer within the alternating stack, wherein the semiconductor pedestal is laterally spaced from the backside blocking dielectric layer by a tubular semiconductor oxide spacer.

13. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of vertical semiconductor channels having a same structure as the vertical semiconductor channel, wherein at least one end portion of each of the plurality of vertical semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

14. A three-dimensional memory device c

Assignees

• Sandisk Technologies Llc

Inventors

• Ge Chun
• Zhang Yanli
• Alsmeier Johann
• Yu Fabo
• Yu Jixin

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11529

  Electricity · mapped topic