Alignment testing for tiered semiconductor structure

Patent metadata

Field	Value
Publication number	US-10073135-B2
Application number	US-201715601226-A
Country	US
Kind code	B2
Filing date	May 22, 2017
Priority date	Oct 25, 2013
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.

First claim

What is claimed is:

1. A method for evaluating a tiered semiconductor structure, comprising:
evaluating connectivity, through a conductive arc within a first layer of a tiered semiconductor structure, between a first via, a second via, and a third via of a second layer of the tiered semiconductor structure to determine an alignment rotation, wherein the evaluating connectivity comprises:
transmitting a first test signal through the first via and measuring a response at the second via and the third via to yield first results, and
transmitting a second test signal through the second via and measuring a response at the first via and the third via to yield second results;

evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation; and
invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

2. The method of claim 1 , the evaluating connectivity comprising:
determining a degree to which the conductive arc is rotated relative to a specified orientation of the conductive arc, the first via, the second via, and the third via to determine the alignment rotation.

3. The method of claim 1 , wherein the third via is disposed between the first via and the second via.

4. The method of claim 1 , the evaluating connectivity comprising:
determining the alignment rotation using the first results and the second results.

5. The method of claim 1 , wherein:
the conductive arc comprises a first arc segment having a first end and a second end,
the first end is separated from the second end by a second arc segment that is non-conductive,
the first via, the second via, and the third via are formed within the second layer and arranged along a third arc segment spanning from the first via to the third via and having a length equal to a length of the second arc segment,
the second via is disposed between the first via and the third via, and
when the first layer is aligned with the second layer, the first via contacts the first end of the conductive arc and the third via contacts the second end of the conductive arc.

6. The method of claim 5 , wherein the second via is in contact with the second arc segment when the tiered semiconductor structure is aligned.

7. The method of claim 5 , wherein the first via, the second via, and the third via are evenly spaced along the third arc segment.

8. The method of claim 5 , wherein:
the evaluating connectivity comprises:
determining the alignment rotation using the first results and the second results, and

the evaluating the tiered semiconductor structure for misalignment comprises:
determining whether the second layer is misaligned with the first layer based upon the alignment rotation.

9. A method for evaluating a tiered semiconductor structure, comprising:
evaluating connectivity within a first arc segment of a conductive arc, wherein:
the conductive arc is within a first layer of a tiered semiconductor structure and the connectivity is evaluated between a set of vias within a second layer of the tiered semiconductor structure, and

the evaluating connectivity comprises:
transmitting a first test signal through a first via of the set of vias and measuring a response at a second via of the set of vias adjacent to the first via and a third via of the set of vias adjacent to the second via to yield first results, and
transmitting a second test signal through the second via and measuring a response at the first via and the third via to yield second results;

responsive to determining that the first via has connectivity through the first arc segment to the second via, that the first via does not have connectivity to the third via, and that the second via does not have connectivity to the third via, determining a counterclockwise alignment rotation;
evaluating the tiered semiconductor structure for misalignment based upon the counterclockwise alignment rotation; and
invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

10. The method of claim 9 , wherein the first arc segment has a first end separated from a second end.

11. The method of claim 10 , wherein a second arc segment that is non-conductive is disposed between first end and the second end.

12. The method of claim 11 , wherein:
the first via, the second via, and the third via are arranged along a third arc segment spanning from the first via to the third via, and
a length of the second arc segment is equal to a length of the third arc segment such that when the tiered semiconductor structure is aligned, the first via contacts the first end of the conductive arc and the third via contacts the second end of the conductive arc.

13. The method of claim 9 , wherein the determining that the first via has connectivity through the first arc segment to the second via, that the first via does not have connectivity to the third via, and that the second via does not have connectivity to the third via comprises:
determining that the first test signal was transmitted through the first via and the first arc segment to the second via; and
determining that the first test signal was not transmitted to the third via.

14. A method for evaluating a tiered semiconductor structure, comprising:
evaluating connectivity within a first arc segment of a conductive arc, wherein:
the conductive arc is within a first layer of a tiered semiconductor structure and the connectivity is evaluated between a set of vias within a second layer of the tiered semiconductor structure, and
the evaluating connectivity comprises:
transmitting a first test signal through a first via of the set of vias and measuring a response at a second via of the set of vias adjacent to the first via and a third via of the set of vias adjacent to the second via to yield first results, and
transmitting a second test signal through the second via and measuring a response at the first via and the third via to yield second results;

responsive to determining that the third via has connectivity through the first arc segment to the second via, that the first via does not have connectivity to the third via, and that the first via does not have connectivity to the second via, determining a clockwise alignment rotation value;
evaluating the tiered semiconductor structure for misalignment based upon the clockwise alignment rotation value; and
invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.

15. The method of claim 14 , wherein the determining that the third via has connectivity through the first arc segment to the second via, that the first via does not have connectivity to the third via, and that the first via does not have connectivity to the second via comprises:
determining that the second test signal was transmitted through the second via and the first arc segment to the third via; and
determining that the first test signal was not transmitted to the third via.

16. The method of claim 14 , wherein the first arc segment has a first end separated from a second end by a third arc segment.

17. The method of claim 16 , wherein:
the set of vias are arranged along a second arc segment spanning from the first via to the third via, and
a length of the second arc segment is equal

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Mill-Jer
• Peng Ching-Nen
• Lin Hung-Chih
• Chen Hao
• Lee Mincent

Classifications

• G01R31/54

  Testing for continuity · CPC title

• G01R31/66

  Testing of connections, e.g. of plugs or non-disconnectable joints (testing for incorrect line connections G01R31/55) · CPC title

• G01R31/2601

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title

• G01B2210/56

  Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth · CPC title

• G01R31/318513

  Test of Multi-Chip-Moduls · CPC title