Two-step interconnect testing of semiconductor dies

Patent metadata

Field	Value
Publication number	US-9678142-B2
Application number	US-201414247019-A
Country	US
Kind code	B2
Filing date	Apr 7, 2014
Priority date	Apr 8, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.

First claim

What is claimed is:

1. A method of testing an interconnect in a semiconductor die, comprising:
providing the semiconductor die, wherein the semiconductor die comprises:
a first interconnect-under-test arranged between a first electrical contact element and a second electrical contact element, and
a second interconnect-under-test arranged between a third electrical contact element and a fourth electrical contact element,
wherein the second interconnect-under-test is connected to the first interconnect-under test via an electrical component;

testing a first signal path in the semiconductor die for manufacturing defects, the first signal path comprising a first part of the first interconnect-under-test and a first deviation path from the first interconnect-under-test through the electrical component to the third electrical contact element, thus obtaining first test results, wherein testing the first signal path comprises probing the first electrical contact element and the third electrical contact element;
testing a second signal path in the semiconductor die for manufacturing defects, the second signal path comprising a second part of the first interconnect-under-test and a second deviation path from the first interconnect-under-test through the electrical component to the fourth electrical contact element, thus obtaining second test results, wherein testing the second signal path comprises probing the second electrical contact element and the fourth electrical contact element;
determining whether or not the first interconnect-under-test suffers from manufacturing defects from the first and second test results; and
determining whether or not the second interconnect-under-test suffers from manufacturing defects from the first and second test results,
wherein the first electrical contact element and the third electrical contact element are formed at a first major surface on the same side of the semiconductor die.

2. The method of claim 1 ,
wherein the first interconnect-under-test comprises a first vertical interconnection between the first electrical contact element and the second electrical contact element formed at a second major surface of the semiconductor die on an opposite side of the first major surface, and
wherein the second interconnect-under-test comprises a second vertical interconnection between the third electrical contact element and the fourth electrical contact element formed at the second major surface of the semiconductor die.

3. The method of claim 2 , wherein testing the second signal path further comprises testing a path between the second electrical contact element and the third electrical contact element.

4. The method of claim 1 ,
wherein the first interconnect-under-test comprises a first horizontal interconnection between the first and second electrical contact elements formed at the first major surface of the semiconductor die, and
wherein the second interconnect-under-test comprises a second horizontal interconnection between the third and fourth electrical contact elements formed at the first major surface of the semiconductor die.

5. The method of claim 4 , wherein testing the second signal path comprises testing a path between the second and third electrical contact elements.

6. The method of claim 1 , wherein testing the first signal path includes measuring a characteristic of the electrical component.

7. The method of claim 1 , wherein the semiconductor die is an active-lite interposer comprising passive and active device components.

8. The method of claim 7 , wherein the active-lite interposer is provided, prior to thinning and stacking, with a plurality of vertical interconnects that are buried in a wafer, wherein probing on the first electrical contact element and on the third electrical contact element is performed at a wafer front end, wherein, during probing on the first electrical contact element and on the third electrical contact element, an electrical characterization is performed on the electrical element to determine that a vertical path from the first electrical contact element to the electrical element and from the third electrical contact element to the electrical element exists.

9. The method of claim 8 , wherein, after probing on the first electrical contact element and on the third electrical contact element, through-silicon vias (TSVs) of the active-lite interposer are exposed, by thinning the active-interposer, and provided with the second and fourth electrical contact elements, wherein, during probing on the second electrical contact element and on the fourth electrical contact element, an electrical characterization is performed on the electrical element to determine that a vertical path from the second electrical contact element to the electrical element and from the fourth electrical contact element to the electrical element exists.

10. The method of claim 9 , further comprising mounting the thinned interposer temporarily on a temporary carrier.

11. A semiconductor die adapted to be tested for manufacturing defects, the semiconductor die comprising:
a surface having a plurality of electrical contact elements;
a first interconnect-under-test between a first electrical contact element and a second electrical contact element;
a second interconnect-under-test between a third electrical contact element and a fourth electrical contact element,
wherein the second interconnect-under-test is connected to the first interconnect-under test via an electrical component;
a first signal path in the semiconductor die configured for testing for manufacturing defects by obtaining first test results, the first signal path comprising a first part of the first interconnect-under-test and a first deviation path from the first interconnect-under-test through the electrical component to the third electrical contact element, wherein the first signal path is configured to be tested by probing the first electrical contact element and the third electrical contact element;
second signal path in the semiconductor die configured for testing for manufacturing defects by obtaining second test results, the second signal path comprising a second part of the first interconnect-under-test and a second deviation path from the first interconnect-under-test through the electrical component to the fourth electrical contact element, wherein the second signal path is configured to be tested by probing the second electrical contact element and the fourth electrical contact element;
wherein at least three of the first electrical contact element, the second electrical contact element, the third electrical contact element and the fourth electrical contact element are formed at a first major surface on the same side of the semiconductor die.

12. The semiconductor die of claim 11 ,
wherein the first interconnect-under-test comprises a first horizontal interconnection between the first and second electrical contact elements formed at the first major surface of the semiconductor die.

13. The semiconductor die of claim 12 , wherein the second interconnect-under-test comprises a second horizontal interconnection between the third a electrical contact element and the fourth electrical element each formed at the first major surface of the semiconductor die.

14. The semiconductor die of claim 11 , wherein the first interconnect-under-test comprises a vertical interconnection between the first electrical contact element at the first major surface of the semiconductor die and a second electrical contact element at a second major surface of the semiconductor die opposite to the first major surface.

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Assignees

• Imec

Inventors

• Ryckaert Julien
• Marinissen Erik Jan
• Linten Dimitri

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title