Organic light-emitting diode display and method of driving the same

Patent metadata

Field	Value
Publication number	US-10068530-B2
Application number	US-201615283588-A
Country	US
Kind code	B2
Filing date	Oct 3, 2016
Priority date	Oct 5, 2015
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

Provided are an organic light-emitting diode (OLED) display and method of driving the same. An OLED display includes: a display panel including a plurality of pixels, each pixel including an OLED, an emission timing of each pixel being controlled in response to an EM signal, a shift register configured to generate an anti-phase EM signal based on gate shift clocks, and an inverter configured to: invert a phase of the anti-phase EM signal based on emission shift clocks, and generate the EM signal, wherein a driving frequency of the shift register and a driving frequency of the inverter are lower in a low-speed driving mode than in a normal driving mode, and wherein in the low-speed driving mode, an amplitude of the emission shift clocks is less than an amplitude of the gate shift clocks.

First claim

What is claimed is:

1. An organic light-emitting diode (OLED) display, comprising:
a display panel comprising a plurality of pixels, each pixel comprising an OLED, an emission timing of each pixel being controlled in response to an EM signal;
a shift register configured to generate an anti-phase EM signal based on gate shift clocks; and
an inverter configured to:
invert a phase of the anti-phase EM signal based on emission shift clocks; and
generate the EM signal,

wherein a driving frequency of the shift register and a driving frequency of the inverter are both lower in a low-speed driving mode than in a normal driving mode, and
wherein, in the low-speed driving mode, an amplitude of the emission shift clocks is less than an amplitude of the gate shift clocks.

2. The display of claim 1 , wherein:
the shift register is further configured to supply the anti-phase EM signal to an input node of the inverter through an output line; and
the inverter comprises a ripple suppression capacitor connected between the input node and an input terminal of a gate low voltage, the ripple suppression capacitor being configured to suppress a ripple on the anti-phase EM signal.

3. The display of claim 1 , wherein, in the low-speed driving mode:
the gate shift clocks swing between a gate high voltage and a gate low voltage;
the emission shift clocks swing between the gate high voltage and a first gate low voltage; and
a level of the first gate low voltage is greater than a level of the gate low voltage.

4. The display of claim 1 , wherein, in the low-speed driving mode:
the gate shift clocks swing between a gate high voltage and a gate low voltage;
the emission shift clocks swing between a first gate high voltage and the gate low voltage; and
a level of the first gate high voltage is less than a level of the gate high voltage.

5. The display of claim 1 , wherein the inverter comprises:
a plurality of switches comprising a plurality of series-connected switch pairs, at least one of the switches among the plurality of switches having a gate connected to the gates of at least one pair among the plurality of series-connected switch pairs; and
a boosting capacitor having one end connected between at least two pairs among the plurality of series-connected switch pairs.

6. The display of claim 1 , wherein the inverter comprises:
a first switch comprising:
a gate electrode connected to a boosting capacitor at a storage node;
a drain electrode connected to an input terminal of a gate high voltage; and
a source electrode connected to an output node;

a second switch comprising:
a gate electrode connected to a first intermediate node;
a drain electrode connected to the output node; and
a source electrode connected to a second intermediate node;

a third switch comprising:
a gate electrode connected to the first intermediate node;
a drain electrode connected to the second intermediate node; and
a source electrode connected to an input terminal of a gate low voltage;

a fourth switch comprising:
a gate electrode connected to an input terminal of an emission shift clocks;
a drain electrode connected to the input terminal of the gate high voltage; and
a source electrode connected to the storage node;

a fifth switch comprising:
a gate electrode connected to an input node;
a drain electrode connected to the storage node; and
a source electrode connected to the input terminal of the gate low voltage;

a sixth switch comprising:
a gate electrode connected to the output node;
a drain electrode connected to the input terminal of the gate high voltage; and
a source electrode connected to the second intermediate node.

7. An organic light-emitting diode (OLED) display, comprising:
a display panel comprising a plurality of pixels, each pixel comprising an OLED, an emission timing of each pixel being controlled in response to an EM signal;
a shift register configured to generate an anti-phase EM signal based on gate shift clocks; and
an inverter configured to:
invert a phase of the anti-phase EM signal based on emission shift clocks; and
generate the EM signal,

wherein the shift register is further configured to supply the anti-phase EM signal to an input node of the inverter through an output line,
wherein the inverter comprises a ripple suppression capacitor connected between the input node and an input terminal of a gate low voltage, the ripple suppression capacitor being configured to suppress a ripple on the anti-phase EM signal,
wherein a driving frequency of the shift register and a driving frequency of the inverter are both lower in a low-speed driving mode than in a normal driving mode, and
wherein, in the low-speed driving mode, an amplitude of the emission shift clocks is less than an amplitude of the gate shift clocks.

8. The display of claim 7 , wherein, in the low-speed driving mode:
the gate shift clocks swing between a gate high voltage and a gate low voltage;
the emission shift clocks swing between the gate high voltage and a first gate low voltage; and
a level of the first gate low voltage is greater than a level of the gate low voltage.

9. The display of claim 7 , wherein, in the low-speed driving mode:
the gate shift clocks swing between a gate high voltage and a gate low voltage;
the emission shift clocks swing between a first gate high voltage and the gate low voltage; and
a level of the first gate high voltage is less than a level of the gate high voltage.

10. The display of claim 7 , wherein the inverter further comprises:
a plurality of switches comprising a plurality of series-connected switch pairs, at least one of the switches among the plurality of switches having a gate connected to the gates of at least one pair among the plurality of series-connected switch pairs; and
a boosting capacitor CB having one end connected between at least two pairs among the plurality of series-connected switch pairs.

11. The display of claim 7 , wherein the inverter further comprises:
a first switch comprising:
a gate electrode connected to a boosting capacitor at a storage node;
a drain electrode connected to an input terminal of a gate high voltage; and
a source electrode connected to an output node;

a second switch comprising:
a gate electrode connected to a first intermediate node;
a drain electrode connected to the output node; and
a source electrode connected to a second intermediate node;

a third switch comprising:
a gate electrode connected to the first intermediate node;
a drain electrode connected to the second intermediate node; and
a source electrode connected to an input terminal of a gate low voltage;

a fourth switch comprising:
a gate electrode connected to an input terminal of an emission shift clocks;
a drain electrode connected to the input terminal of the gate high voltage; and
a source electrode connected to the storage node;

a fifth switch comprising:
a gate electrode connected to an input node;
a drain electrode connected to the storage node; and
a source electrode connected to the input terminal of the gate low voltage;

a sixth switch comprising:
a gate electrode connected to the output node;
a drain electrode connected to the input terminal of the gate high voltage; and
a source electrode connected to the second intermediate node.

12. A method of driving an organic light-emitting diode (OLED) display including a display panel having a plurality of pixels, each pixel including an OLED, an emission timing of each pixel being controlled in response to an EM signal, the method comprising:
generating, by a shift register, an anti-phase EM signal

Assignees

• Lg Display Co Ltd

Inventors

• Lee Youngjang
• YOON Jeanhan

Classifications

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title