Display Device Capable Of Driving At Low Speed

Patent metadata

Field	Value
Publication number	US-2015187308-A1
Application number	US-201414308387-A
Country	US
Kind code	A1
Filing date	Jun 18, 2014
Priority date	Dec 31, 2013
Publication date	Jul 2, 2015
Grant date	—

Abstract

A display device capable of driving at low speed is disclosed. Pixels connected to a first data line on odd-numbered display lines of a display panel are positioned on one side of the left and right sides of the first data line, and pixels connected to the first data line on even-numbered display lines of the display panel are positioned on the other side of the first data line based on a Z-inversion scheme. When a mode conversion control signal for switching to an interlaced low speed driving mode is input during a normal drive, in which a length of one frame is set to P, a timing controller expands a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2 and assigns a length P to each of n sub-frames of the one frame.

First claim

What is claimed is:

1 . A display device capable of driving at low speed, which changes a frame frequency in response to a mode conversion control signal, the display device comprising:
a display panel, on which a plurality of pixels are formed, pixels connected to a first data line on odd-numbered display lines of the display panel being positioned on one side of the left and right sides of the first data line based on a Z-inversion scheme, pixels connected to the first data line on even-numbered display lines of the display panel being positioned on the other side of the first data line based on the Z-inversion scheme; a driver unit configured to drive the plurality of pixels; and a timing controller configured to, responsive to the mode conversion control signal for switching to an interlaced low speed driving mode being received during a normal drive, in which a length of one frame is set to P:
expand a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2,
assign a length P to each of n sub-frames included in the one frame for the low speed drive,
group a plurality of display line pairs each including two adjacent display lines into n groups, resulting in n display line pair groups, and
respectively drive the n display line pair groups in the n sub-frames in an interlaced low speed driving scheme by controlling an operation of the driver unit.

2 . The display device of claim 1 , wherein the driver unit includes a gate driver for driving gate lines of the display panel and a source driver for driving data lines of the display panel,
wherein in the interlaced low speed driving mode, the timing controller: groups a plurality of gate line pairs each including two adjacent gate lines into n groups,
respectively drives the n gate line pair groups in the n sub-frames in the interlaced low speed driving scheme by controlling an operation of the gate driver,
completes a scanning operation, during a scan period, of gate lines belonging to a corresponding gate line pair group occupying a portion of one sub-frame,
generates a buffer operation control signal, and
shuts off a driving power source applied to buffers of the source driver during a skip period corresponding to a remaining period excluding the scan period from the one sub-frame.

3 . The display device of claim 2 , wherein in the interlaced low speed driving mode, the timing controller changes a polarity control signal, expands a polarity inversion period of a data voltage, for input to the display panel, to one frame for the low speed drive, controls an operation of the source driver, outputs the data voltage to the data lines during the scan period, and skips an output of the data voltage during the skip period.

4 . The display device of claim 3 , wherein the source driver outputs data voltages of opposite polarities through adjacent output channels in a column inversion scheme and inverts a polarity of each output channel in a cycle of one frame for the low speed drive in response to the polarity control signal.

5 . The display device of claim 2 , wherein the scan period occupies 1/n of each sub-frame, and the skip period following the scan period occupies (n−1)/n of each sub-frame.

6 . The display device of claim 2 , wherein the timing controller sets one gate time required to scan one gate line in each sub-frame to ‘1H’ defined by the length P of one sub-frame/the number of gate lines and sets a distance between rising edges of adjacent scan pulses scanned in an interlaced scheme in one sub-frame to ‘1H’, so as to secure the skip period in the interlaced low speed driving mode.

7 . The display device of claim 2 , wherein a scanning operation of the gate driver and a data voltage supply operation of the source driver are skipped during the skip period of each sub-frame.

Assignees

• Lg Display Co Ltd

Inventors

• Shin Seunghwan
• Park Yonghwa
• Oh Daeseok
• Chung Moonsoo

Classifications

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G3/2022

  using sub-frames · CPC title

• G09G2310/0224

  Details of interlacing · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title