Display backplane and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9490276-B2
Application number	US-201414231586-A
Country	US
Kind code	B2
Filing date	Mar 31, 2014
Priority date	Feb 25, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide semiconductor) while at least one of the TFTs implementing the driving circuit next to the active area is a LTPS TFT (i.e., TFT with poly-Si semiconductor).

First claim

What is claimed is:

1. A display comprising:
a pixel circuit formed on a thin-film-transistor (TFT) backplane having an oxide TFT layer and a low-temperature-poly-silicon (LTPS) TFT layer on a same substrate, the pixel circuit comprising:
an organic light emitting diode (OLED) between a first supply voltage line of a first voltage and a second supply voltage line of a second voltage lower than the first voltage, and
a driving TFT including the oxide TFT layer, the driving TFT connected to the first supply voltage line and coupled in series with the OLED to the second supply voltage line, a gate of the driving TFT coupled to a data line to receive a data signal.

2. The display of claim 1 , wherein the TFT backplane includes an active area and a non-display area, the pixel formed on the active area of the TFT backplane, wherein a gate driver is formed on the non-display area of the TFT backplane, the gate driver configured to supply a gate signal to the pixel circuit.

3. The display of claim 1 , wherein the pixel circuit further comprises:
a first switching TFT having a terminal connected to a first node, the first node being connected to a storage capacitor and the gate of the driving TFT;
a second switching TFT having a terminal connected to a second node, the second node being connected to a first terminal of the driving TFT and the OLED; and
a third switching TFT having a first terminal connected to the first supply voltage line and a second terminal connected to a second terminal of the driving TFT, wherein the third switching TFT includes the LTPS TFT layer.

4. The display of claim 3 , wherein the third switching TFT is a P-Type TFT including the LTPS TFT layer, the P-type TFT configured to supply the first supply voltage from the first supply voltage line to the second terminal of the driving TFT when a gate signal of the second voltage is applied to a gate of the third switching TFT.

5. The display of claim 3 , wherein the first switching TFT and the second switching TFT include the oxide TFT layer, and wherein the driving TFT includes the LTPS TFT layer.

6. The display of claim 3 , wherein the storage capacitor includes a first storage capacitor and a second storage capacitor that are serially connected to each other.

7. The display of claim 6 , wherein the first storage capacitor is formed between the gate of the driving TFT and a source of the driving TFT, and wherein the second storage capacitor is formed between the source of the driving TFT and the second terminal of the third switching TFT.

8. The display of claim 6 , wherein the first storage capacitor is formed between the gate of the driving TFT and the first terminal of the driving TFT, and wherein the second storage capacitor is formed between the first terminal of the driving TFT and an initial voltage line supplying an initialization voltage.

9. The display of claim 6 , wherein the first storage capacitor is formed between the gate of the driving TFT and the first terminal of the driving TFT, and wherein the second storage capacitor is formed between the first terminal of the driving TFT and the second supply voltage line supplying the second voltage.

10. The display of claim 1 , wherein the TFT backplane includes a plurality of pixel circuits and one driving circuit implemented on the same substrate, wherein the driving circuit includes one oxide TFT including the oxide TFT and one LTPS TFT including the LTPS TFT layer.

11. The display of claim 10 , wherein the driving circuit that includes the one oxide TFT and the LTPS TFT is a gate driver for supplying a plurality of gate signals to a plurality of pixel circuits, the plurality of pixel circuits including the pixel circuit.

12. The display of claim 10 , wherein the driving circuit that includes the oxide TFT and the LTPS TFT is an invert circuit coupled to a gate driver for inverting at least one gate signal to a plurality of pixel circuits, the plurality of pixel circuits including the pixel circuit.

13. The display of claim 10 , wherein the driving circuit that includes the oxide TFT and the LTPS TFT is a switching circuit coupled to a gate driver for controlling output of at least one gate signal to a plurality of pixel circuits, the plurality of pixel circuits including the pixel circuit.

14. The display of claim 1 , wherein the pixel circuit further comprises a switching TFT including the LTPS TFT layer, the switching TFT coupled in series with the first supply voltage line, the driving TFT and the OLED.

15. The display of claim 3 , wherein the third switching TFT and the driving TFT are coupled in series between the first supply voltage line and the second supply voltage line, wherein the third switching TFT is a P-Type TFT and the driving TFT is an N-type TFT.

16. A display comprising:
a pixel circuit formed on a thin-film transistor (TFT) backplane having an oxide TFT and a low-temperature-poly-silicon (LTPS) TFT on a same substrate, the pixel circuit including at least one oxide TFT and at least one LTPS TFT, which are connected in parallel to each other.

17. The display of claim 16 , wherein gates of said at least one oxide TFT and said at least one LTPS TFT connected in parallel to each other are connected to a same data line.

18. The display of claim 17 , wherein drains of said at least one oxide TFT and at least one LTPS TFT are coupled to each other, and sources of said at least one oxide TFT and at least one LTPS TFT are coupled to each other.

19. The display of claim 17 , wherein said at least one oxide TFT is coupled in series between (i) a voltage line for supplying a supply voltage and (ii) an organic light emitting diode (OLED) and said at least one LTPS TFT is coupled in series between (i) the voltage line and (ii) the OLED.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Hyoung-Su
• Cho Namwook
• Kim Taehwan
• Lee Jaemyon

Classifications

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/421 Primary

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H10D86/471 Primary

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title