Display device configured to be driven in one of a plurality of modes

Patent metadata

Field	Value
Publication number	US-9542889-B2
Application number	US-201414478530-A
Country	US
Kind code	B2
Filing date	Sep 5, 2014
Priority date	Jan 8, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A display device is disclosed. In one aspect, the display device includes a timing controller configured to receive an image signal and a control signal and output a mode signal and a gate pulse signal based on the image signal and the control signal, wherein the mode signal has a voltage level and wherein the gate pulse signal has a frequency. The display device further includes a clock generator configured to generate a gate clock signal based on the mode signal and the gate pulse signal, wherein the gate clock signal has a voltage level and wherein the clock generator is further configured to set the voltage level of the gate clock signal based at least in part on the mode signal. The display device includes gate lines and a gate driver configured to drive gate lines based at least in part on the gate clock signal.

First claim

What is claimed is:

1. A display device, comprising:
a plurality of data lines;
a data driver configured to drive the data lines;
a plurality of gate lines;
a display panel including a plurality of pixels connected to the data lines and the gate lines;
a timing controller configured to i) receive an image signal and a control signal and ii) output a mode signal and a gate pulse signal based at least in part on the image signal and the control signal, wherein the mode signal has a voltage level and wherein the gate pulse signal has a frequency;
a clock generator configured to generate a gate clock signal based at least in part on the mode signal and the gate pulse signal, wherein the gate clock signal has a voltage level and wherein the clock generator is further configured to set the voltage level of the gate clock signal based at least in part on the mode signal; and
a gate driver configured to drive the gate lines based at least in art on the gate clock signal,
wherein the timing controller is further configured to set the frequency of the gate pulse signal and the voltage level of the mode signal based at least in part on the image signal, and
wherein the voltage level of the mode signal comprises first and second voltage levels different from each other, wherein the gate clock signal is configured to swing between a gate-on voltage and a first ground voltage when the mode signal has the second voltage level, and wherein the gate clock signal is configured to swing between the gate-on voltage and a second ground voltage when the mode signal has the first voltage level.

2. The display device of claim 1 , wherein the timing controller is further configured to:
set the mode signal to the first voltage level when the image signal is a moving image; and
set the mode signal to the second voltage level when the image signal is a still image.

3. The display device of claim 2 , wherein the frequency of the gate pulse signal comprises a first frequency and a second frequency less than the first frequency, wherein the gate pulse signal has the first frequency when the mode signal has the first voltage level, and wherein the gate pulse signal has the second frequency when the mode signal has the second voltage level.

4. The display device of claim 1 , further comprising a voltage generator configured to generate the gate-on voltage, the first ground voltage, and the second ground voltage.

5. The display device of claim 4 , wherein the gate lines are divided into a plurality of first gate lines and a plurality of second gate lines and wherein the gate driver comprises:
a first gate driver configured to drive the first gate lines; and
a second gate driver configured to drive the second gate lines.

6. The display device of claim 5 , wherein the timing controller is further configured to generate a start pulse signal and wherein the first gate driver comprises a plurality of stages respectively corresponding to the first gate lines, wherein each stage is configured to i) receive the gate clock signal, a previous-stage carry signal, a next-stage carry signal, the first ground voltage, and the second ground voltage and ii) output a carry signal and a gate signal based at least in part on the received signals; wherein the stages include:
a dummy stage configured to i) receive the start pulse signal as the next-stage carry signal and ii) output a dummy carry signal and a dummy gate signal based at least in part on the received signals; and
a first stage configured to receive the start pulse signal as the previous-stage carry signal, and
wherein the previous-stage carry signal is the carry signal output from a previous stage and the next-stage carry signal is the carry signal output from a next stage.

7. The display device of claim 6 , wherein the second ground voltage is substantially equal to the first ground voltage when the mode signal has the second voltage level.

8. The display device of claim 6 , wherein the clock generator is further configured to generate a reset signal and set the reset signal to a first level when the mode signal has the second voltage level and wherein each of the stages of the first gate driver comprises:
a first reset transistor having a gate terminal electrically connected to the reset signal, wherein the first reset transistor is electrically connected between i) a first output terminal configured to output the carry signal and ii) the first ground voltage; and
a second reset transistor having a gate terminal electrically connected to the reset signal, wherein the second reset transistor is electrically connected between i) a second output terminal configured to output the gate signal and ii) the first ground voltage.

9. The display device of claim 5 , wherein the clock generator is further configured to generate an inverted gate clock signal that is inverted with respect to the gate clock signal, wherein the timing controller is further configured to generate a start pulse signal, and wherein the second gate driver comprises a plurality of stages respectively corresponding to the second gate lines, wherein each stage is configured to i) receive the gate clock signal, a previous-stage carry signal, a next-stage carry signal, the first ground voltage, and the second ground voltage and ii) output a carry signal and a gate signal based at least in part on the received signals; and wherein the stages include:
a dummy stage configured to i) receive the start pulse signal as the next-stage carry signal and ii) output a dummy carry signal and a dummy gate signal based at least in part on the received signals; and
a first stage is configured to receive the start pulse signal as the previous-stage carry signal,
wherein the previous-stage carry signal is a carry signal output from a previous stage and the next-stage carry signal is a carry signal output from a next stage.

10. The display device of claim 9 , wherein the second ground voltage is substantially equal to the first ground voltage when the mode signal has the second voltage level.

11. The display device of claim 9 , wherein the clock generator is further configured to generate a reset signal and set the reset signal to a first level when the mode signal has the second voltage level and wherein each of the stages of the second gate driver comprises:
a first reset transistor having a gate terminal electrically connected to the reset signal, wherein the first reset transistor is electrically connected between i) a first output terminal configured to output the carry signal and ii) the first ground voltage; and
a second reset transistor having a gate terminal electrically connected to the reset signal, wherein the second reset transistor is electrically connected between i) a second output terminal configured to output the gate signal and ii) the first ground voltage.

12. The display device of claim 5 , wherein the first gate driver is arranged adjacent to a first short edge of the display panel and wherein the second gate driver is arranged adjacent to a second short edge of the display panel.

13. The display device of claim 5 , wherein the first gate lines and the second gate lines are alternately arranged.

14. The display device of claim 1 , further comprising a plurality of final-stage reset transistors respectively corresponding to the gate lines, wherein each final-stage reset transistor has a gate terminal electrically connected to an immediately adjacent gate line, and wherein each final-stage reset transistor is electrically connected between the corresponding gate line and the first ground voltage.

15. The display device of

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Cheol-Gon
• Shin Kyoungju
• Chai Chongchul
• Kim Hyunjoon
• Lim Jaekeun

Classifications

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2320/103

  Detection of image changes, e.g. determination of an index representative of the image change · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2310/0213

  controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power · CPC title

• G09G2300/0413

  Details of dummy pixels or dummy lines in flat panels · CPC title