Trench gate trench field plate vertical MOSFET

Patent metadata

Field	Value
Publication number	US-10062777-B2
Application number	US-201715485892-A
Country	US
Kind code	B2
Filing date	Apr 12, 2017
Priority date	Oct 3, 2013
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

First claim

What is claimed is:

1. A vertical drain extended transistor formed in a semiconductor substrate, comprising:
a first trench structure comprising:
a first trench;
a first insulating liner formed on sides and bottom of the first trench; and
a first conductive material operable to have an electrical potential and formed on the first insulating liner;

a second trench structure comprising:
a second trench;
a second insulating liner formed on sides and bottom of the second trench; and
a second conductive material operable to have said electrical potential and formed on the second insulating liner;

a gate structure comprising:
a gate trench;
a gate dielectric layer on sides and bottom of the gate trench; and
a polysilicon gate on the gate dielectric layer in the gate trench, wherein the gate structure is spaced apart from the first trench structure and the second trench structure, wherein no trench structure is located between the first trench structure and the gate structure or between the second trench structure and the gate structure;

an n-type vertically oriented drift region extending below the gate structure, wherein the first trench structure and the second trench structure are deeper than a top of the n-type vertically oriented drift layer;
a p-type body region type over the n-type vertically extended drift region, contacting the gate dielectric layer at a side of the gate trench; and
an n-type source region over the p-type body region, contacting to the gate dielectric layer at the side of the gate trench and extending to a surface of the semiconductor substrate between the first trench structure and the gate structure.

2. The vertical drain extended transistor of claim 1 , wherein the first conductive material is electrically coupled to the n-type source region.

3. The vertical drain extended transistor of claim 1 , wherein the semiconductor substrate includes an epitaxial layer, and the first trench structure, the second trench structure and the gate structure are formed in the epitaxial layer.

4. The vertical drain extended transistor of claim 1 , wherein the first trench structure and the second trench structure are 0.5 to 1.5 microns wide.

5. The vertical drain extended transistor of claim 1 , wherein the gate dielectric layer comprises silicon dioxide.

6. The vertical drain extended transistor of claim 1 , wherein the gate dielectric layer is comprised of silicon dioxide and aluminum oxy-nitride.

7. The vertical drain extended transistor of claim 1 , wherein the first conductive material and the second conductive material comprise polysilicon.

8. The vertical drain extended transistor of claim 1 , wherein the p-type body region is a first p-type body region, the n-type source region is a first n-type source region, the n-type vertically oriented drift region is a first n-type vertically oriented drift region, and further comprising:
a second p-type body region over the vertically extended drift region, contacting the gate dielectric layer at an opposite side of the gate trench; and
a second n-type source region over the second p-type body region, contacting to the gate dielectric layer at the opposite side of the gate trench and extending to the surface of the semiconductor substrate between the second trench structure and the gate structure.

9. The vertical drain extended transistor of claim 8 , wherein the gate structure is a first gate structure and further comprising:
a second gate structure;
a third trench structure comprising:
a third trench;
a third insulating liner formed on sides and bottom of the third trench; and
a third conductive material operable to have said electrical potential and formed on the third insulating liner, wherein the second gate structure is spaced apart from the second trench structure and the third trench structure;

a second n-type vertically oriented drift region;
a third p-type body region over the second n-type vertically oriented drift region, contacting one side of the second gate structure; and
a third n-type source region over the third p-type body region, contacting the one side of the second gate structure and extending to the surface of the semiconductor substrate between the third trench structure and the second gate structure,
wherein the third trench structure is deeper than a top of the second n-type vertically oriented drift region.

10. The vertical drain extended transistor of claim 9 , wherein the third conductive material is electrically coupled to the third n-type source region.

Assignees

• Texas Instruments Inc

Inventors

• Denison Marie
• Pendharkar Sameer
• Mathur Guru

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H01L29/7813 Primary

  Electricity · mapped topic

• H01L29/063

  Electricity · mapped topic