Semiconductor device and method for manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9231100-B2
Application number	US-201213664792-A
Country	US
Kind code	B2
Filing date	Oct 31, 2012
Priority date	Oct 31, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A semiconductor device is at least partially formed in a semiconductor substrate, the substrate including first and second opposing main surfaces. The semiconductor device includes a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, the cell field portion including at least a transistor. The contact area includes a connection substrate portion insulated from other substrate portions and including a part of the semiconductor substrate, an electrode adjacent to the second main surface and in contact with the connection substrate portion, and a metal layer disposed over the first main surface, the connection substrate portion being electrically coupled to the metal layer to form an ohmic contact between the electrode and metal layer. The connection substrate portion is not electrically coupled to a component of the cell field portion by a conductive material disposed between the first and second main surfaces.

First claim

What is claimed is:

1. A semiconductor device, being at least partially formed in a semiconductor substrate, the semiconductor substrate comprising a first and a second main surface, the first and the second main surfaces being opposed to each other, the semiconductor device comprising a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, the cell field portion comprising at least a transistor, the contact area comprising:
a connection substrate portion insulated from other substrate portions and comprising a part of the semiconductor substrate, the connection substrate portion not being electrically coupled to a component of the cell field portion by means of the semiconductor substrate;
an electrode adjacent to the second main surface and in contact with the connection substrate portion; and
a metal layer disposed over the first main surface, the connection substrate portion being electrically coupled to the metal layer to form a contact between the electrode and the metal layer.

2. The semiconductor device according to claim 1 , further comprising an insulating layer disposed between the first main surface and the metal layer, and a conductive element, the connection substrate portion being electrically coupled to the metal layer via the conductive element.

3. The semiconductor device according to claim 2 , wherein the conductive element comprises a trench formed in the first main surface, the trench being filled with a conductive material.

4. The semiconductor device according to claim 3 , further comprising a doped substrate portion adjacent to the second main surface, wherein the trench extends to the doped substrate portion.

5. The semiconductor device according to claim 1 , further comprising isolation trenches extending from the first main surface to the second main surface, wherein the connection substrate portion is insulated from other substrate portions by the isolation trenches.

6. The semiconductor device according to claim 5 , wherein the isolation trenches are filled with a conductive material insulated from the semiconductor substrate.

7. The semiconductor device according to claim 5 , wherein the transistor of the cell field portion comprises a source region, a drain region and a gate electrode, and wherein the conductive material inside the isolation trenches is electrically coupled to the gate electrode.

8. The semiconductor device according to claim 5 , wherein the transistor in the cell field portion comprises a source region, a drain region and a gate electrode, and wherein the conductive material of the isolation trenches is electrically coupled to the source region.

9. The semiconductor device according to claim 1 , wherein the transistor of the cell field portion comprises a source region, a drain region and a gate electrode.

10. The semiconductor device according to claim 9 , wherein the source region is adjacent to the first main surface and the drain region is adjacent to the second main surface, the semiconductor device further comprising a source electrode formed by a metal layer disposed over the first main surface, the source electrode being electrically coupled to the source region.

11. The semiconductor device according to claim 9 , wherein the gate electrode is disposed in a trench formed in the first main surface of the semiconductor substrate, the gate electrode being electrically coupled to the metal layer over the first main surface.

12. The semiconductor device according to claim 11 , further comprising a drain electrode formed by a metal layer disposed over the second main surface, the drain electrode being electrically coupled to the drain region.

13. The semiconductor device according to claim 11 , wherein the gate electrode is electrically coupled to the metal layer over the first surface via a gate contact trench.

14. A semiconductor device, being at least partially formed in a semiconductor substrate, the semiconductor substrate comprising a first and a second main surface, the first and the second main surfaces being opposed to each other, the semiconductor device comprising a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, the cell field portion comprising at least a transistor, the contact area comprising:
a connection substrate portion insulated from other substrate portions and comprising a part of the semiconductor substrate;
an electrode adjacent to the second main surface and in contact with the connection substrate portion;
a metal layer disposed over the first main surface, the connection substrate portion being electrically coupled to the metal layer to form a contact between the electrode and the metal layer;
an insulating layer disposed between the first main surface and the metal layer; and
a trench formed in the first main surface, the trench being filled with a conductive material, the connection substrate portion being electrically coupled to the metal layer via the trench.

15. The semiconductor device according to claim 14 , further comprising a doped substrate portion adjacent to the second main surface, wherein the trench extends to the doped substrate portion.

16. A semiconductor device, being at least partially formed in a semiconductor substrate, the semiconductor substrate comprising a first and a second main surface, the first and the second main surfaces being opposed to each other, the semiconductor device comprising a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, the cell field portion comprising at least a transistor, the contact area comprising:
a connection substrate portion insulated from other substrate portions and comprising a part of the semiconductor substrate, the connection substrate portion not being electrically coupled to a component of the cell field portion by means of the semiconductor substrate;
isolation trenches extending from the first main surface to the second main surface, wherein the connection substrate portion is insulated from other substrate portions by the isolation trenches;
an electrode adjacent to the second main surface and in contact with the connection substrate portion; and
a metal layer disposed over the first main surface, the connection substrate portion being electrically coupled to the metal layer to form a contact between the electrode and the metal layer.

Assignees

• Infineon Technologies Austria

Inventors

• Meiser Andreas
• Schloesser Till
• Poelzl Martin

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title