Vertical channel-type 3D semiconductor memory device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9613981-B2
Application number	US-201615214372-A
Country	US
Kind code	B2
Filing date	Jul 19, 2016
Priority date	Dec 13, 2012
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the method includes depositing alternating insulating and electrode layers on a substrate to form a multi-layer film. The method further includes etching the film to the substrate to form through-holes, each of which defines a channel region. The method further includes depositing barrier, storage, and tunnel layers in sequence on inner walls of through-holes to form gate stacks. The method further includes depositing and incompletely filling a channel material on a surface of the tunnel layer of gate stacks to form a hollow channels. The method further includes forming drains in contact hole regions for bit-line connection in top portions of the hollow channels. The method further includes forming sources in contact regions between the through-holes and the substrate in bottom portions of the hollow channels.

First claim

What is claimed:

1. A method of manufacturing a vertical channel-type 3D semiconductor memory device, comprising:
depositing alternating layers of at least one insulating layer and at least one electrode material layer on a substrate to form a multi-layer film;
etching the multi-layer film to the substrate to form a plurality of through-holes, each of which defines a respective channel region;
depositing a barrier layer, a storage layer, and a tunnel layer in sequence on an inner wall of a respective one of the plurality of through-holes to form a plurality of gate stacks;
depositing and incompletely filling a channel material on a surface of the tunnel layer of a respective one of the plurality of gate stacks to form a plurality of hollow channels;
forming a plurality of drains in respective contact hole regions for bit-line connection in respective top portions of the plurality of hollow channels; and
forming a plurality of sources in respective contact regions between the plurality of through-holes and the substrate in respective bottom portions of the plurality of hollow channels.

2. The method of claim 1 , wherein each of the plurality of hollow channels has a column, annular, or strip shape, and/or wherein the channel material is selected from the group consisting of polysilicon, amorphous silicon, Ge—Si, Ge, GaAs, and InGaAs.

3. The method of claim 2 , further comprising forming each of the plurality of hollow channels by depositing a polysilicon film directly on the surface of a respective one of the tunnel layers.

4. The method of claim 2 , further comprising forming each the plurality of hollow channels by depositing an amorphous silicon film on the surface of a respective one of the tunnel layers, followed by high-temperature annealing.

5. The method of claim 1 , wherein each of the plurality of gate stacks is a charge capturing-type memory gate stack based on separate charge storage or a floating gate-type memory gate stack based on continuous storage medium.

6. The method of claim 5 , wherein the charge capturing-type memory gate stack comprises:
a tunnel layer;
a separate dielectric storage layer; and
a barrier layer.

7. The method of claim 6 , wherein the separate dielectric storage layer comprises SiN or a high-K dielectric material of HfO.

8. The method of claim 5 , wherein the floating gate-type memory gate stack comprises:
a tunnel layer;
a storage layer; and
a barrier layer.

9. The method of claim 8 , wherein the storage layer comprises polysilicon, metal, or a combination of polysilicon and metal.

10. The method of claim 1 further comprising performing a surface process on respective surfaces of the plurality of hollow channels to reduce defective states at the respective surfaces.

11. The method of claim 10 , wherein performing the surface process comprises annealing in nitrogen gas so as to reduce dangling bonds at the respective surfaces of the plurality of hollow channels.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Huo Zongliang
• Liu Ming

Classifications

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title