Vertical memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9324730-B2
Application number	US-201514601496-A
Country	US
Kind code	B2
Filing date	Jan 21, 2015
Priority date	Jan 22, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate including first regions on sides of a second region;
a plurality of channels in the first regions, respectively, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate;
a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate;
a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and
a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode in each of the first regions.

2. The vertical memory device as claimed in claim 1 , wherein the first regions and the second region are arranged alternately in the second direction, each of the first regions and the second region extending in the third direction.

3. The vertical memory device as claimed in claim 2 , wherein the supporter has a width in the second direction that is substantially identical to a width of the second region, and the supporter has a length in the third direction that is substantially identical to or larger than the width of the second region.

4. A vertical memory device comprising:
a substrate including first regions and a second region;
a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate;
a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate;
a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and
a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode,
wherein:
the gate electrodes include a ground selection line (GSL), a word line and a string selection line (SSL) that are sequentially arranged from the top surface of the substrate,
a bottom surface of the supporter is substantially lower than a bottom surface of the SSL, and
the bottom surface of the supporter is substantially higher than a top surface of the word line.

5. The vertical memory device as claimed in claim 1 , wherein:
the gate electrodes include a ground selection line (GSL), a word line and a string selection line (SSL) that are sequentially arranged from the top surface of the substrate, and
a bottom surface of the supporter directly contacts a top surface of the SSL.

6. The vertical memory device as claimed in claim 1 , wherein the supporter includes silicon oxide or polysilicon.

7. The vertical memory device as claimed in claim 1 , wherein:
the supporter includes a second supporter and a first supporter surrounding a bottom surface and a sidewall of the second supporter,
the first supporter includes silicon oxide, and
the second supporter includes polysilicon.

8. The vertical memory device as claimed in claim 1 , further comprising:
insulation layer patterns between the gate electrodes in the first direction,
wherein the supporter directly contacts sidewalls of the insulation layer patterns, and the supporter holds the insulation layer patterns.

9. The vertical memory device as claimed in claim 1 , further comprising:
an impurity region at an upper portion of the substrate in the second region, the impurity region extending in the third direction.

10. The vertical memory device as claimed in claim 9 , further comprising:
a contact in the second region, the contact extending in the first direction, and directly contacting a top surface of the impurity region.

11. A vertical memory device comprising:
a substrate including first regions and a second region;
a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate;
a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate;
a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction;
a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode;
an impurity region at an upper portion of the substrate in the second region, the impurity region extending in the third direction; and
a contact in the second region, the contact extending in the first direction, and directly contacting a top surface of the impurity region,
wherein the contact penetrates the supporter.

12. A method of manufacturing a vertical memory device, the method comprising:
forming a plurality of sacrificial layers and a plurality of insulation layers on a substrate alternately and repeatedly, the substrate having first regions on sides of a second region;
forming a supporter in the second region, the supporter penetrating at least one sacrificial layer and at least one insulation layer;
forming holes through the sacrificial layers and the insulation layers to expose a top surface of the substrate in the first regions;
forming a charge storage structure and a channel filling each hole;
partially removing the sacrificial layers and the insulation layers to form an opening, the opening exposing a top surface of the substrate in the second region;
forming a plurality of gaps by removing the sacrificial layers to expose a sidewall of each charge storage structure; and
forming a gate electrode to fill each gap, the supporter contacting a sidewall of the gate electrode in each of the first regions.

13. The method as claimed in claim 12 , wherein the supporter prevents the insulation layers from leaning during the steps of forming the opening and forming the gaps.

14. The method as claimed in claim 12 , wherein:
forming the gate electrode includes:
forming a preliminary gate electrode layer on an inner wall of the opening, the preliminary gate electrode layer including a metal;
performing a heat treatment process such that the preliminary gate electrode layer and a remaining portion of the sacrificial layers are transformed into a gate electrode layer; and
partially removing the gate electrode layer, and

forming the plurality of gaps includes partially removing the sacrificial layers, the sacrificial layers including polysilicon.

15. The method as claimed in claim 12 , wherein the supporter includes a silicon oxide or polysilicon.

16. A vertical memory device, comprising:
a substrate including first regions situated on each side of a second region;
at least one channel in the first regions, respectively the at least one channel extending in a first direction substantially perpendicular to a top surface of the substrate;

Assignees

• Nam Phil-Ouk
• Yoo Dong-Chul
• Kim Bi-O
• Ahn Jae-Young
• Jang Byong-Hyun
• Hwang Ki-Hyun
• Samsung Electronics Co Ltd

Inventors

• Nam Phil-Ouk
• Yoo Dong-Chul
• Kim Bi-O
• Ahn Jae-Young
• Jang Byong-Hyun
• Hwang Ki-Hyun

Classifications

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic