Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-9147652-B2
Application number	US-201414281662-A
Country	US
Kind code	B2
Filing date	May 19, 2014
Priority date	Apr 25, 2008
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127 , respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117 , respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.

First claim

What is claimed is:

1. A layout structure of a standard cell, comprising:
a first metal interconnect for providing a first power potential, the first metal interconnect extending in a first direction;
a second metal interconnect for providing a second power potential, the second metal interconnect extending in the first direction;
a logic circuit disposed between the first metal interconnect and the second metal interconnect, and including a metal interconnect and a transistor…

Assignees

• Panasonic Corp
• Socionext Inc

Inventors

• Okamoto Nana
• Tamaru Masaki
• Nishimura Hidetoshi

Classifications

• H10W70/635 Primary

  Electricity · mapped topic

• H10D89/10

  Electricity · mapped topic

• H10D84/907 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic