Semiconductor device having a memory and calibration circuit that adjusts output buffer impedance dependent upon auto-refresh commands

Patent metadata

Field	Value
Publication number	US-9378799-B2
Application number	US-201514720524-A
Country	US
Kind code	B2
Filing date	May 22, 2015
Priority date	Sep 11, 2009
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first control circuit configured to produce a hit signal in response to an internal refresh command being issued;
a second control circuit configured to produce a control signal in response to the hit signal being produced, the control signal changing between first and second levels in response to temperature information indicative of a temperature of the semiconductor device;
a memory cell array including a plurality of memory cells;
an output buffer coupled to the memory cell array and configured to output data read from the memory cells;
a calibration circuit coupled to the output buffer and configured to perform, when activated, a calibration operation on the output buffer to adjust an impedance of the output buffer;
a refresh circuit coupled to the memory cell array and configured to perform a refresh operation on the memory cells of the memory cell array in response to the internal refresh command; and
a third control circuit configured to issue the internal refresh command when the control signal takes the first level and to activate the calibration circuit in response to the hit signal when the control signal takes the second level.

2. The semiconductor device as claimed in claim 1 , wherein the third control circuit is configured to issue the internal refresh command without triggering a production of the hit signal.

3. The semiconductor device as claimed in claim 1 , wherein the second control circuit activates the calibration circuit each time an auto refresh command has issued for a predetermined number of times.

4. The semiconductor device as claimed in claim 1 , wherein the third control circuit is configured to deactivate the calibration circuit to refrain from performing the calibration operation when the control signal takes the first level.

5. The semiconductor device as claimed in claim 4 , wherein the third control circuit is configured to not issue the internal refresh command to refrain from performing the refresh operation when the control signal takes the second level.

6. The semiconductor device as claimed in claim 1 , wherein the refresh circuit includes a counter configured to count a number of issuance of the refresh command, and wherein the first control circuit includes:
an address register configured to store an address; and
a comparator configured to compare the address stored in the address register with an address corresponding to the number of issuance of the refresh command and to output the hit signal when the address stored in the address register and the address corresponding to the number of issuance of the refresh command are coincident with each other.

7. The semiconductor device as claimed in claim 6 , wherein the comparator of the first control circuit is configured to refrain from outputting the hit signal when the address stored in the address register and the address corresponding to the number of issuance of the refresh command are different from each other.

8. The semiconductor device as claimed in claim 1 , wherein a number of calibration operations performed by the calibration circuit is changed according to a scale of a temperature change detected for the semiconductor device.

9. The semiconductor device as claimed in 8 , wherein a larger number of calibration operations is performed as the detected temperature change becomes larger.

10. The semiconductor device as claimed in claim 1 , wherein the second control circuit is configured to check a content of the temperature information each time the hit signal is produced.

11. The semiconductor device as claimed in claim 10 , wherein the second control circuit is configured to change the control signal from one of the first and second levels to the other of the first and second levels, when the temperature information upon a preceding production of the hit signal is different in content from the temperature information upon a current production of the hit signal.

12. The semiconductor device as claimed in claim 11 , wherein the second control circuit includes:
a temperature detection circuit configured to generate the temperature information of the semiconductor device;
a first register coupled to the temperature detection circuit to receive the temperature information upon the current production of the hit signal; and
a second register coupled to the first register to receive the temperature information upon the preceding production of the hit signal.

13. The semiconductor device as claimed in claim 12 , wherein the second control circuit further includes a comparator coupled to the first and second registers to compare a content of the temperature information upon the current production of the hit signal with a content of the temperature information upon the preceding production of the hit signal.

14. The semiconductor device as claimed in claim 11 , wherein the temperature information comprises first and second temperature bits, the first temperature bit taking one of the first and second levels when the temperature of the semiconductor device is equal to or higher than a first degree and the other of the first and second levels when the temperature of the semiconductor device is lower than the first degree, the second temperature bit taking one of the first and second levels when the temperature of the semiconductor device is equal to or higher than a second degree and the other of the first and second levels when the temperature of the semiconductor device is lower than the second degree, the first degree and the second degree being different from each other.

15. The semiconductor device as claimed in claim 14 , wherein the control signal takes the second level during a first period of time when the first temperature bit of the temperature information upon the preceding production of the hit signal and the first temperature bit of the temperature information upon the current production of the hit signal are different from each other, the control signal taking the second level during a second period of time when the first temperature bit of the temperature information upon the preceding production of the hit signal and the first temperature bit of the temperature information upon the current production of the hit signal are equal to each other and the second temperature bit of the temperature information upon the preceding production of the hit signal and the second temperature bit of the temperature information upon the current production of the hit signal are different from each other, the first period of time and the second period of time being different from each other.

16. The semiconductor device as claimed in claim 15 , wherein the first degree is higher than the second degree and the first period of time is longer than the second period of time.

17. The semiconductor device as claimed in claim 1 , wherein the hit signal is produced by the first control circuit each time the internal refresh command is issued.

Assignees

• Ps4 Luxco S A R I
• Ps4 Luxco Sarl

Inventors

• Kaiwa Nakaba
• Ikeda Yutaka
• Fujisawa Hiroki
• Okahiro Tetsuaki

Classifications

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C2211/4061

  Calibration or ate or cycle tuning · CPC title

• G11C11/406 Primary

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title