Structure and method for narrowing voltage threshold distribution in non-volatile memories
US-8988940-B2 · Mar 24, 2015 · US
Nonvolatile memory devices including simultaneous impedance calibration and input command
US9361985B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9361985-B2 |
| Application number | US-201314144659-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 31, 2013 |
| Priority date | Jan 2, 2013 |
| Publication date | Jun 7, 2016 |
| Grant date | Jun 7, 2016 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration operation; and if the input command sequence accompanies the impedance calibration operation, simultaneously performing an operation corresponding to the input command sequence and the impedance calibration operation.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory device, comprising: a memory cell array; a control logic configured to detect whether an input command sequence for performing a read operation of the memory cell array, a program operation of the memory cell array, or an erase operation of the memory cell array accompanies an impedance calibration operation; an impedance calibration circuit connected with an external reference resistor and configured to generate an impedance calibration code in…
Assignees
Inventors
Classifications
Physics · mapped topic
Physics · mapped topic
- G11C7/04Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9361985B2 cover?
- An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration operation; and if the input command sequence accompanies the impedance calibration operation, simultaneously performing an operation corresponding to the input command sequence and the impedance calibration …
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G11C7/04. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jun 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).