Protocol for memory power-mode control

Patent metadata

Field	Value
Publication number	US-9502096-B2
Application number	US-201414573323-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	Feb 23, 2011
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

First claim

What is claimed is:

1. A method of controlling a memory device that includes a memory core, the method comprising:
providing a self-refresh command to the memory device; and
after providing the self-refresh command to the memory device and the memory device receiving the self-refresh command, providing a control signal to the memory device, wherein, in response to the self-refresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

2. The method of claim 1 , wherein the control signal specifies entry into a power mode in which input receivers of the memory device are powered down.

3. The method of claim 2 , further comprising providing to the memory device, a value that specifies whether a subset of input receivers are powered down in response to the control signal.

4. The method of claim 2 , further comprising providing to the memory device, control information that specifies whether a subset of the input receivers are powered down in response to the control signal.

5. A memory device comprising:
a core of dynamic random access memory cells that are refreshed during a self-refresh operation; and
an interface to receive a self-refresh command, wherein, in response to the interface of the memory device receiving the self-refresh command, the self-refresh operation is initiated upon receipt of a control signal that is received after the interface receives the self-refresh command.

6. The memory device of claim 5 , wherein the control signal specifies entry into a power mode in which input receivers of the memory device are powered down.

7. The memory device of claim 6 , wherein the input receivers include input receivers to receive the self-refresh command and input receivers to receive data; and
wherein the interface is configured to receive a value that specifies whether a subset of the input receivers are powered down in response to the control signal.

8. The memory device of claim 7 , wherein the value specifies that the subset of the input receivers are the input receivers to receive data.

9. The memory device of claim 6 , wherein the input receivers include input receivers to receive the self-refresh command and input receivers to receive data; and
wherein the interface is configured to receive control information that specifies whether a subset of the input receivers are powered down in response to the control signal.

10. A memory controller comprising:
a first interface to provide a self-refresh command to a memory device; and
a second interface to provide to the memory device, after providing the self-refresh command and the memory device receiving the self-refresh command, a control signal, which allows the memory device, in response to the self-refresh command, to defer entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

11. The memory controller of claim 10 , wherein the control signal specifies entry into a power mode in which input receivers of the memory device are powered down.

12. The memory controller of claim 11 , wherein the first interface is configured to provide to the memory device, a value that specifies whether a subset of input receivers are powered down in response to the control signal.

13. The memory controller of claim 11 , wherein the first interface is configured to provide to the memory device, control information that specifies whether a subset of the input receivers are powered down in response to the control signal.

Assignees

• Rambus Inc

Inventors

• Ellis Wayne F
• Richardson Wayne S
• Bansal Akash
• Ware Frederick A
• Lai Lawrence
• Kasamsetty Kishore Ven

Classifications

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title