Metal nitride keyhole or spacer phase change memory cell structures

US10056546B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10056546-B2
Application numberUS-201715489368-A
CountryUS
Kind codeB2
Filing dateApr 17, 2017
Priority dateFeb 27, 2014
Publication dateAug 21, 2018
Grant dateAug 21, 2018

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Abstract

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Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of dielectric material and in the via opening. A phase change material structure is present in the via opening and contacting a top portion of each sidewall surface of the layer of dielectric material and a topmost surface of each metal nitride spacer. A top electrode is located on a topmost surface of the phase change material structure.

First claim

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What is claimed is: 1. A non-volatile memory cell comprising: a layer of dielectric material having a via opening and located above a bottom electrode; a keyhole forming material spacer located in the via opening and contacting sidewall surfaces of said layer of dielectric material, said keyhole forming material spacer having a topmost surface that is coplanar with a topmost surface of said layer of dielectric material and a bottommost surface directly contacting a portion of a topmost surface of said bottom electrode; a wrap around bottom electrode metal nitride contact located in a bottom of said via opening and contacting another portion of said topmost surface of said bottom electrode, wherein said wrap around bottom electrode metal nitride contact has a bottommost surface that is coplanar with said bottommost surface of said keyhole forming material spacer; a phase change material structure present within said via opening; and a top electrode located on a topmost surface of said phase change material. 2. The non-volatile memory cell of claim 1 , wherein said wrap around bottom electrode metal nitride contact comprises a compound M-X—N wherein M is Ti or Ta, and X is Al or Si. 3. The non-volatile memory cell of claim 1 , wherein said phase change memory material structure comprises a chalcogenide. 4. The non-volatile memory cell of claim 1 , further comprising a contiguous surfactant liner located between said keyhole forming material spacer and said phase change material structure and between said wrap around bottom electrode metal nitride contact and said phase change material structure. 5. The non-volatile memory cell of claim 1 , further comprising a surfactant spacer located directly on vertical sidewall surfaces of said keyhole forming material spacer and on directly on vertical sidewalls of said wrap around bottom electrode metal nitride contact. 6. The non-volatile memory cell of claim 5 , further comprising a contiguous surfactant liner located directly on sidewalls of said surfactant spacer, and on exposed horizontal surfaces of each keyhole forming material spacer and further on exposed horizontal surfaces of said wrap around bottom electrode metal nitride contact. 7. The non-volatile memory cell of claim 6 , wherein said surfactant spacer comprises aluminum nitride, boron nitride, aluminum oxide, tantalum nitride, tungsten, tungsten nitride, cobalt tungsten, nickel tungsten, yttrium oxide or any combination thereof. 8. The non-volatile memory cell of claim 6 , wherein said contiguous surfactant liner comprises aluminum nitride, boron nitride, aluminum oxide, tantalum nitride, tungsten, tungsten nitride, cobalt tungsten, nickel tungsten, yttrium oxide or any combination thereof. 9. The non-volatile memory cell of claim 1 , further comprising a surfactant spacer located directly on vertical sidewall surfaces of said keyhole forming material spacer and contacting only a top horizontal surface of said wrap around bottom electrode metal nitride contact. 10. The non-volatile memory cell of claim 9 , further comprising a surfactant liner that is contiguous and that is located directly on sidewall surfaces of said surfactant spacer and directly on surfaces of said wrap around bottom electrode metal nitride contact. 11. The non-volatile memory cell of claim 9 , wherein said surfactant spacer comprises aluminum nitride, boron nitride, aluminum oxide, tantalum nitride, tungsten, tungsten nitride, cobalt tungsten, nickel tungsten, yttrium oxide or any combination thereof. 12. The non-volatile memory cell of claim 9 , wherein said contiguous surfactant liner comprises aluminum nitride, boron nitride, aluminum oxide, tantalum nitride, tungsten, tungsten nitride, cobalt tungsten, nickel tungsten, yttrium oxide or any combination thereof. 13. A non-volatile memory cell comprising: a layer of dielectric material having a via opening and located above a bottom electrode; a keyhole forming material spacer located in the via opening and contacting sidewall surfaces of said layer of dielectric material, the keyhole forming material spacer having a topmost surface that is coplanar with a topmost surface of said layer of dielectric material; a wrap around bottom electrode metal nitride contact located in a bottom of said via opening and contacting another portion of said topmost surface of said bottom electrode; a phase change material structure present within said via opening; and a top electrode located on a topmost surface of said phase change material, wherein said bottom electrode includes a recessed region and a portion of said wrap around bottom electrode metal nitride contact is present in said recessed region. 14. A non-volatile memory cell comprising: a layer of dielectric material having a via opening and located above a a bottom electrode; a keyhole forming material spacer located in the via opening and contacting sidewall surfaces of said layer of dielectric material, said keyhole forming material spacer having a topmost surface that is coplanar with a topmost surface of said layer of dielectric material; a surfactant spacer located on sidewall surfaces of said keyhole forming material spacer; a contiguous surfactant liner located on sidewall surfaces of said surfactant and on a portion of a surface of said bottom electrode not covered by said surfactant spacer; a phase change material structure present within said via opening; and a top electrode located on a topmost surface of said phase change material. 15. The non-volatile memory cell of claim 14 , wherein said phase change memory material structure comprises a chalcogenide. 16. The non-volatile memory cell of claim 14 , wherein said surfactant spacer comprises aluminum nitride, boron nitride, aluminum oxide, tantalum nitride, tungsten, tungsten nitride, cobalt tungsten, nickel tungsten, yttrium oxide or any combination thereof. 17. The non-volatile memory cell of claim 14 , wherein said contiguous surfactant liner comprises aluminum nitride, boron nitride, aluminum oxide, tantalum nitride, tungsten, tungsten nitride, cobalt tungsten, nickel tungsten, yttrium oxide or any combination thereof. 18. The non-volatile memory cell of claim 14 , wherein said topmost surface of said keyhole forming material spacer, said surfactant spacer, and said contiguous surfactant liner are coplanar with a topmost surface of said phase change material structure.

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What does patent US10056546B2 cover?
Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01L45/124. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 21 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).