Test structure for monitoring interface delamination

Patent metadata

Field	Value
Publication number	US-10056306-B2
Application number	US-201615015478-A
Country	US
Kind code	B2
Filing date	Feb 4, 2016
Priority date	Feb 4, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

First claim

We claim:

1. A test structure comprising:
two or more devices, wherein each device includes:
a wire disposed within a dielectric;
a first via disposed over the wire and in electrical contact with the wire;
a second via disposed under the wire and over a polysilicon resistor and in electrical contact with the wire and the polysilicon resistor;
a test pad electrically connected to the first via; and
the polysilicon resistor electrically connected to the wire,

wherein each of the polysilicon resistors of the two or more devices are electrically tied together.

2. The test structure of claim 1 , wherein the first via and the second via of each device are offset by at least 0.5 microns.

3. The test structure of claim 1 , wherein the second via of each device has a height of at least 2 microns.

4. The test structure of claim 1 , wherein the first via of each device is selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag).

5. The test structure of claim 1 , wherein the second via of each device is selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag).

6. The test structure of claim 1 , wherein a wire of each device is selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag).

7. The test structure of claim 1 , wherein the test structure is disposed within a kerf of a wafer.

8. The test structure of claim 1 , wherein the first via of each device has a height of at least 2 microns.

9. The test structure of claim 1 , wherein the wire of each device has a height of at least 2 microns.

10. The test structure of claim 2 , wherein the test structure is disposed within a kerf of a wafer.

11. The test structure of claim 3 , wherein the test structure is disposed within a kerf of a wafer.

12. The test structure of claim 1 , wherein: the first via of each device is selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag); the second via of each device is selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag); and wherein the wire is selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag).

13. The test structure of claim 12 , wherein the test structure is disposed within a kerf of a wafer.

14. The test structure of claim 1 , wherein the first via and the second via of each device has a height of at least 2 microns.

15. The test structure of claim 14 , wherein the test structure is disposed within a kerf of a wafer.

16. The test structure of claim 2 , wherein: the first via of each device is selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag); the second via of each device is selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag); and wherein the wire is selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag).

17. The test structure of claim 16 , wherein the test structure is disposed within a kerf of a wafer.

18. The test structure of claim 2 , wherein the first via and the second via of each device has a height of at least 2 microns.

19. The test structure of claim 18 , wherein the test structure is disposed within a kerf of a wafer.

20. A test structure comprising:
two or more devices disposed within a kerf of a wafer, wherein each device includes:
a wire selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag) having a height of at least 2 microns disposed within a dielectric;
a first via having a height of at least 2 microns selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag) disposed over the wire and in electrical contact with the wire;
a second via having a height of at least 2 microns selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), and silver (Ag) disposed under the wire and over the polysilicon resistor and in electrical contact with the wire and the polysilicon resistor, wherein the first via and the second via on a device are offset by at least 0.5 microns;
a test pad electrically connected to the first via; and
a polysilicon resistor electrically connected to the wire,

wherein each of the polysilicon resistors of the two or more devices are electrically tied together.

Assignees

• Globalfoundries Inc

Inventors

• Cooney Iii Edward C
• Milo Gary L
• Weeks Thomas W
• Spinney Patrick S
• Hall John C
• Conchieri Brian P
• Cucci Brett T
• Lee Thomas C

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• H01L22/32 Primary

  Electricity · mapped topic