Oxide semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10043917-B2
Application number	US-201615059311-A
Country	US
Kind code	B2
Filing date	Mar 3, 2016
Priority date	Mar 3, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, agate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

First claim

What is claimed is:

1. A method of processing oxide-semiconductor devices, comprising:
providing a substrate;
forming oxide-semiconductor devices of same type on said substrate;
forming an insulating layer over said oxide-semiconductor devices and said substrate;
performing a chemical mechanical planarization process to said insulating layer so that said insulating layer has a flat top surface;
forming a first mask which defines a first implantation region on said insulating layer, wherein said first implantation region encompasses a plurality of said oxide-semiconductor devices;
performing a first oxygen implantation process on said first implantation region;
removing said first mask;
forming a second mask which defines a second implantation region on said insulating layer, wherein said second implantation region encompasses a plurality of said oxide-semiconductor devices;
performing a second oxygen implantation process on said second implantation region;
patterning said insulating layer so that only said oxide-semiconductor devices are covered by said patterned insulating layer in both of the first implantation region and the second implantation region, wherein each of the individual patterned insulating layers is coextensive with a lateral width of each of said oxide semiconductor devices; and
forming a top blocking film over said patterned insulating layer.

2. The method of processing oxide-semiconductor devices of claim 1 , further comprising an annealing process after said second oxygen implantation process.

3. The method of processing oxide-semiconductor devices of claim 1 , further comprising the step of forming an inter-metal dielectric over said top blocking film.

4. The method of processing oxide-semiconductor devices of claim 1 , wherein said oxide-semiconductor devices in said first implantation region and said oxide-semiconductor devices in said second implantation region are different in width/length ratios.

5. The method of processing oxide-semiconductor devices of claim 1 , wherein the number of said oxide-semiconductor devices per area in said first implantation region is more than the number of said oxide-semiconductor devices per area in said second implantation region.

6. The method of processing oxide-semiconductor devices of claim 5 , wherein said oxide-semiconductor devices in said first implantation region and said oxide-semiconductor devices in said second implantation region have same pattern dimension.

7. The method of processing oxide-semiconductor devices of claim 1 , wherein said first oxygen implantation process and said second oxygen implantation process have different oxygen dosages.

8. The method of processing oxide-semiconductor devices of claim 1 , wherein said top blocking film has a blocking effect against oxygen, hydrogen and water, and is made of a metal nitride.

Assignees

• United Microelectronics Corp

Inventors

• Zhou Zhibiao
• Wu shao-hui
• Lin Chen-Bin
• Chen Ding-Lung
• Ku Chi-Fa

Classifications

• H10P30/22

  using masks · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H01L29/78648

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic