Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9214474-B2
Application number	US-201213535506-A
Country	US
Kind code	B2
Filing date	Jun 28, 2012
Priority date	Jul 8, 2011
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

To provide a transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use and provide a semiconductor device including the transistor, in a transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating film, and a gate electrode are stacked in this order over an oxide semiconductor insulating film, an oxide semiconductor stack layer which includes at least two oxide semiconductor layers with energy gaps different from each other and a mixed region therebetween is used as the semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
an oxide semiconductor stack layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer;
a source electrode layer and a drain electrode layer over the oxide semiconductor stack layer;
a gate insulating film over the source electrode layer and the drain electrode layer; and
a gate electrode layer over the gate insulating film, the gate electrode layer overlapping with the oxide semiconductor stack layer,
wherein the second oxide semiconductor layer is between the first oxide semiconductor layer and the third oxide semiconductor layer,
wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer,
wherein a first mixed region whose composition is different from a composition of the first oxide semiconductor layer and a composition of the second oxide semiconductor layer is between the first oxide semiconductor layer and the second oxide semiconductor layer,
wherein a second mixed region whose composition is different from the composition of the second oxide semiconductor layer and a composition of the third oxide semiconductor layer is between the second oxide semiconductor layer and the third oxide semiconductor layer, and
wherein the third oxide semiconductor layer covers and is in contact with a side surface of the first oxide semiconductor layer and a top surface and a side surface of the second oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein an electron affinity of the second oxide semiconductor layer is higher than an electron affinity of the first oxide semiconductor layer and an electron affinity of the third oxide semiconductor layer.

3. The semiconductor device according to claim 1 , wherein a region of the oxide semiconductor stack layer, which does not overlap with the source electrode layer or the drain electrode layer, has higher oxygen concentration than a region overlapping with the source electrode layer and the drain electrode layer.

4. The semiconductor device according to claim 1 , wherein a region of the oxide semiconductor stack layer, which does not overlap with the gate electrode layer, contains a dopant.

5. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.

6. A semiconductor device comprising:
an oxide semiconductor stack layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer;
a source electrode layer and a drain electrode layer over the oxide semiconductor stack layer;
a gate insulating film over the source electrode layer and the drain electrode layer; and
a gate electrode layer over the gate insulating film, the gate electrode layer overlapping with the oxide semiconductor stack layer,
wherein the second oxide semiconductor layer is between the first oxide semiconductor layer and the third oxide semiconductor layer,
wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer,
wherein a first mixed region whose composition is different from a composition of the first oxide semiconductor layer and a composition of the second oxide semiconductor layer is between the first oxide semiconductor layer and the second oxide semiconductor layer,
wherein a second mixed region whose composition is different from the composition of the second oxide semiconductor layer and a composition of the third oxide semiconductor layer is between the second oxide semiconductor layer and the third oxide semiconductor layer,
wherein the third oxide semiconductor layer covers and is in contact with a side surface of the first oxide semiconductor layer and a top surface and a side surface of the second oxide semiconductor layer, and
wherein each of the source electrode layer and the drain electrode layer is in contact with a side surface of the third oxide semiconductor layer.

7. The semiconductor device according to claim 6 , wherein an electron affinity of the second oxide semiconductor layer is higher than an electron affinity of the first oxide semiconductor layer and an electron affinity of the third oxide semiconductor layer.

8. The semiconductor device according to claim 6 , wherein a region of the oxide semiconductor stack layer, which does not overlap with the source electrode layer or the drain electrode layer, has higher oxygen concentration than a region overlapping with the source electrode layer and the drain electrode layer.

9. The semiconductor device according to claim 6 , wherein a region of the oxide semiconductor stack layer, which does not overlap with the gate electrode layer, contains a dopant.

10. The semiconductor device according to claim 6 , wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.

Assignees

• Yamazaki Shunpei
• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei

Classifications

• H10D30/504

  wherein the stacked channels have different properties · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title